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Explorer
Explorer
7,786 Views
Registered: ‎04-19-2016

What is the 7 - series FPGA output jitter of MMCM or PLL ?

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Hello,

 

I am planning give my ADC (Analog to Digital Converter ) clock input from 7 - Series FPGA (say Artix-7, -2 Speed grade, ftg256 package) by using the internal MMCM or PLL.

 

In order to take a high performance from ADC, a low Jitter clock signal have to be given into it. So I wonder the above Artix-7 FPGA MMCM or PLL output jitter in ps. How does MMCM or PLL effect the output clock jitter ? How much does MMCM or PLL increase the input clock jitter ? 

 

I can not see the Clocking Wizard IP output clocks jitter amount. 

 

Ragards,

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Scholar austin
Scholar
13,540 Views
Registered: ‎02-27-2008

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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d,

 

Best is to not source the clock from the FPGA to the A/D or D/A.  The minimum jitter is something like 50 ps p-p.  Depending on IO switching, what is in the core, etc. the system jitter only gets worse.  A really exceptionally well design board may have 100 ps p-p jitter.  A poorly designed one may have a few hundreds of ps p-p jitter, or even more.

Austin Lesea
Principal Engineer
Xilinx San Jose
8 Replies
Scholar austin
Scholar
13,541 Views
Registered: ‎02-27-2008

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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d,

 

Best is to not source the clock from the FPGA to the A/D or D/A.  The minimum jitter is something like 50 ps p-p.  Depending on IO switching, what is in the core, etc. the system jitter only gets worse.  A really exceptionally well design board may have 100 ps p-p jitter.  A poorly designed one may have a few hundreds of ps p-p jitter, or even more.

Austin Lesea
Principal Engineer
Xilinx San Jose
Explorer
Explorer
7,727 Views
Registered: ‎04-19-2016

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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Hello ,

 

 

Thanks for reply.

 

If I am not wrong, You said the 7- series FPGAs add minimum 50 ps p-p jitter into input clock. This is high for ADC. For the best performance of ADC, it is needed a clock that too lower than 50 ps p-p jitter. Is there a way to see output clock jitter of MMCM or PLL IP in Vivado ? Maybe an output clock jitter can be seen in the timing report ?

 

Clock Wizard IP.jpg  

As you can see above Clock Wizard IP GUI, output clock jitter is not seen and is not adjustable. 

 

Best Regards,

 

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Scholar austin
Scholar
7,725 Views
Registered: ‎02-27-2008

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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In the final timing report, jitter is predicted.

 

set_system_jitter xxx is used to allow the tool to represent the actual jitter, and verify there is sufficient slack,

 

Again, best practice is to use a lowest possible jitter clock distribution scheme (not on the FPGA) to supply the ADC and the FPGA both.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar milosoftware
Scholar
5,089 Views
Registered: ‎10-26-2012

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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Sorry for reviving an old thread.

 

I'm looking for the PLL output jitter estimation but cannot find it anywhere in Vivado's reports.

 

In the final timing report, jitter is predicted

 

Where?

 

The clock driving the PLL has 50ps peak-to-peak jitter, so I set the input clock of the clock wizard accordingly. I cannot find any information on the output jitter though.

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Scholar milosoftware
Scholar
5,079 Views
Registered: ‎10-26-2012

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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I found in the IP documentation that there's a hidden "JITTER" property that can be read with tcl:

 

get_property CONFIG.CLKOUT1_JITTER [get_bd_cells clk_wiz_sample]
324.244

 

Now if only I knew what units are being referred to. Is that 324 picoseconds? Of something else entirely?

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Xilinx Employee
Xilinx Employee
5,075 Views
Registered: ‎02-14-2014

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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Hi @milosoftware,

 

It is 324.244 ps

Regards,
Ashish
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Scholar austin
Scholar
5,068 Views
Registered: ‎02-27-2008

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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It is peak to peak jitter, over all time (worst possible deviation from an otherwise perfect clock),

 

One half of the total jitter (added as the square root of the squares of all jitter components) is subtracted from your period constraints in order to meet timing (worst case clock is that much less time to the next edge).

 

System jitter is set by you, the user to account for all the uncertainties caused by IO switching, power rails, you signal integrity.  It may be as low as 100 ps P-P, or as high as 300 ps P-P, or even greater if your decoupling or power rails are bad.

 

I have seen actual boards with greater than 1000 ps system jitter.

 

After your design is done, and all appears working, I would measure the system jitter, and then enter that value into the tools (TCL set_system_jitter), and the repeat implementation to assure timing is always met.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor nitheesh_m
Visitor
740 Views
Registered: ‎09-13-2018

Re: What is the 7 - series FPGA output jitter of MMCM or PLL ?

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Hello, I'm new to FPGA clocks and jitters. How did you get to run this tcl command I'm getting this error 

ERROR: [BD 5-104] A block design must be open to run this command. Please create/open a block design.

Do I need to change clk_wiz_sample to something in my design if yes please let me know what?

 

thanks a ton.

 

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