08-03-2016 08:17 PM
I am using the XADC on an application where I use the Vaux4 and Vaux12 pairs. My question is, if it is sampling both pairs simultaneously, how do I access the data? From my understanding, you give the XADC the pair address using the address_in pin and the sampled bits are retrieved on the data_out line (which is a single output line). Wouldn't it be necessary to have two data outputs, one for each pair? How does it work?
Thank you guys for your time and patience,
08-03-2016 11:11 PM
08-04-2016 12:16 PM
Thanks for replying, although I still don't quite get it. After I instantiate the adc module using the XADC Wizard in Vivado, this is what I get for a simultaneous sampling instantiation:
input [6:0] daddr_in; input dclk_in; input den_in; input [15:0] di_in; input dwe_in; input reset_in; input vauxp4; input vauxn4; input vauxp12; input vauxn12; input vp_in; input vn_in; output busy_out; output [4:0] channel_out; output [15:0] do_out; output drdy_out; output eoc_out; output eos_out; output alarm_out;
As you can see, there is only one do_out, whereas two ADCs are working simultaneously, generating 12 bits each. Could you shine a light upon this? I don't really get how I am supposed to read the outputs from ADC A and ADC B simultaneously (all I could get was it to work in channel sequencer mode).
09-08-2016 05:37 PM
We (Leo and I) are still having troubles understanding how to retrieve BOTH outputs from the xADC during simultaneous sampling mode. Could some one please explain:
1) In DRP mode, there are 16 output bits (do_out[15:0]). What information is being output for these 16 bits?
2) in AXI4Lite mode, there appear to be 32 output bits (s_axi_rdata[31:0]). What information is being output for these 32 bits?
3) What is the difference between DRP and AXI4Lite?
4) How do we retrieve 12 bits from xADCA and 12 bits from xADCB?
10-25-2016 12:32 PM
So no reply, but since there are 481 views and we figured it out, I figured I would provide an explanation to anyone else stuck on this.
This document should be reviewed thoroughly:
The status registers: 10h to 1Fh (page 38) store the results of the auxiliary input conversions. Therefore, in simultaneous sampling mode, if Aux 4/12 are used, their results are stored in 14h and 1C respectively. In order to access the results, the DRP interface is used. It can read 1 value at a time, therefore, 2 reads are necessary at the end of each conversion in order to obtain the results. Once an EOC event occurs, you may then read the results using the DRP interface. Using the DRP interface is described on page 74.
Also, the xADC IP wizard does not work very well. For example, we desired to have:
The wizard does not allow this even though it is within the specs of the xADC. Therefore, we had to manual program the control registers via the xADC instantiation (the xadc_wiz_'name'.v had to be manually edited) in order to achieve desired operation. For this, the control registers must be analyzed thoroughly (pages 42-47).
05-12-2017 11:53 AM
Just wanted to say thank you for leaving the answer.
I am a novice at FPGA and this really helped me out a lot.