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Adventurer
Adventurer
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Registered: ‎08-04-2018

XADC dual adc data collecting

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Hi guys and @martinwe

 

I have a new question. Now to get data in SIMULTANEOUS SAMPLING MODE. there is only one EOC available and I can provide only 1 address to be read from for this. But to use DUAL ADC and read both after 1 conversion what is the logic? because I tried this and I fail miserable. Because I am trying to use the DUEL adc to achieve full sampling of 1MSPS on both adc. Write now I successfully read data from both the adc on alternating EOC signals. But its like, I loose every second sampling data on each of the adc. If i try to read continuously on only 1adc  while ignoring the other register address. the simulation wont work. It stops abruptly. I use AUX0 (channel: 10000 ; daddr_in: 0010000) and AUX8(channel: 11000 ; daddr_in: 0011000) for my operation.

 

Can you help me please.?

 

 

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

I tried this out on my AC701

So I re-worked the FSM a bit. 

It works fine for me. 

xadc_ss_read2.JPG

 

xadc_ss_read.JPG

 All you have to do now is implement something simple to put the two conversion results onto the same clock edge in the fabric. 

 

 

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13 Replies
Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi

In this case why can't you just read both vaux0 and vaux8 one after the other after the eoc?

It takes 26 ADC clocks(dclk/DCLK divide factor) to complete an conversion so there should be enough time to get both results out before the next conversion result is available.

You would of course have to align the samples to the same clock edge later on in the fabric 

You could also look at the AXI streaming interface. 

Keith

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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I am using DRP for my task, so I have to read from two different registers after the eoc = '1'. Because after the end of conversion when I enable and provide the address to be read from, I can only do for 1 address. How to provide two address? I get error and simulation stops If i try to enable(den = '1') for a second time in the cycle.  

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

You can't do two reads at one time, that was not what I was proposing. 

It takes 26 clocks to do a conversion and you are sampling at 1MSPS. To make it simple, if you have for example a DCLK that is 104mhz and you set the divider to be 4 then it will take 104 DCLK cycles clocks to do one conversion. 

So it should take roughly 4 DCLKs between DEN asserting and DRDY going high. so there is ample time to read from two addresses before the next conversion is done. 

You can convert, read both one after the other and then align them in the fabric. 

Keith  

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Please correct me if I am wrong. My understanding is that when we enable DEN we need to provide the address from which we have top get the data from? then If I can provide only 1 address in the same clock when the DEN is going high, then the DRDY goes high indicating the data to be read is ready from that address. Then in that clock cycle the data is coming out from DO.

I cannot read before the DRDY is going high as you say, nor can I provide 2 address in same clock. To enable the register reads(I have my data in VAUX0 and VAUX8, i.e address "0010000""0011000"). 

 

Please help me. 

xili.PNG
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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

I don' think you understood what I was proposing. 

I know you can't provide it with two addresses or initiate a read while you are awaiting a DRDY, this was not my suggestion.

The point that I was making is that it takes 26 ADC clocks to complete a conversion.

Depending on the DCLK (The example I used was 104Mhz DCLK) for a 1MSPS sample rate then you are talking about 100 DCLK Cycles to do a conversion. 

It takes 4 DCLKs to do a read. 

The result in the register is not going to change. 

So what I am proposing is 

1 EOC goes high

2 Initiate a read on VAUX0 (Store this in a register in the fabric)

3 Wait for DRDY

3 Change the DADDR

4. Initiate a read on VAUX8

5. Do something to allign the previously stored value and the new VAUX8 to the same clock edge in the fabric. 

6.  the remainder of the 100 DCLK cycles elapses. Return to step 1

 

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Can you help me with a test bench design for the same? I am not clear as to how to do it.. I have a sample model, may be you can take the same and help me? Because as seen in th epic the enabling again is not happening. 

Please help me

Thank you

xili.PNG
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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Can you help me out please? Or direct me how to proceed?

 

Thanks in advance.

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

I haven't had much time to spend on this. 

I reckon some DRP state machine like this would work. 

always@(posedge dclk)begin
if(rst)begin
state <= idle;
end
else
state <= next_state;
end

always@* begin
case(state)
idle: begin
den <= 1'b0;
daddr <= 6'h10;
if(eoc)
next_state <= read1;
else
next_state <= idle;
end
read1: begin
den <= 1'b1;
daddr <= 6'h10;
next_state <= wait_on_drdy;
end
read2: begin
den <= 1'b1;
daddr <= 6'h18;
next_state <= wait_on_drdy;
end
wait_on_drdy: begin
den <= 1'b0;
if(drdy && (daddr == 6'h10))
next_state <= read2;
else if(drdy && (daddr == 6'h18))
next_state <= idle;
else
next_state <= wait_on_drdy;
end
endcase
end

 

So roughly:

Wait on EOC do a read of AUX0

Wait for DRDY

move to a state and do a read of AUX8

Wait for DRDY and go back to IDLE and wait on EOC. 

 

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Ok thank you, I will try as you say and get back to you. 

 

Kind regards.

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

I tried this out on my AC701

So I re-worked the FSM a bit. 

It works fine for me. 

xadc_ss_read2.JPG

 

xadc_ss_read.JPG

 All you have to do now is implement something simple to put the two conversion results onto the same clock edge in the fabric. 

 

 

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Sorry for the late Response. I finally managed to retry with the simultaneous mode and here is what I could simulate. 

 

Capture.JPG

If I enable the xadc again I get no data at all... Also I tried to continuously monitor one address for few clocks cycle and later tried to switch to other address, I get no output, just like above.

here is a working model of only one read 

Capture.JPG

I am using the .text file stimulus method. 

architecture Behavioral of control_block is


--signal bus_state : STD_LOGIC;
signal conv_data : STD_LOGIC_VECTOR (15 downto 0);
 
signal s_adc_en : STD_LOGIC := '0';   
signal bus_state : STD_LOGIC_VECTOR (1 downto 0);
signal s_o_DADDR : std_logic_vector(6 downto 0):= "0000000";
signal counter : integer range 0 to 10000 ;
begin

--process to extract data from the xadc component
--sample @ 961.54 ksps
xadc_process: process (clk)
begin
    if rising_edge(clk) then
        
        if i_eoc = '1' then 
            counter <= counter+1;
            s_adc_en <= '1'; 
            o_DADDR <= "0010000";
            s_o_DADDR <= "0010000";                                  
        end if;
        
        --if adc_count = 1 then
            if s_adc_en = '1' then     
                s_adc_en <='0';
                --adc_count <= 2;
            end if; 
        --end if;     
        if i_drdy = '1' then
            conv_data <= i_do;
            s_adc_en <='1';
            o_DADDR <= "0011000";
            s_o_DADDR <= "0011000";
        end if;                          
     end if;           
end process; 
adc_en <= s_adc_en ;  

 

Kindly help me. 

 

Thanks in advance

 

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: XADC dual adc data collecting

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Hi @benaka

 

There is no need to send me private messages about this when I have been already been replying to thread. 

 

You logic here doesn't follow exactly what mine does. 

I didn't run a simulation, I just tried in HW. 

I need to take a closer look. 

 

Keith 

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Adventurer
Adventurer
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Registered: ‎08-04-2018

Re: XADC dual adc data collecting

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Hi @klumsde

 

Thank you for the help. In my case the eoc goes high after the busy goes high. But in yours the busy goes low and the eoc goes high. That is where the confusion was. But If i make the same approach after the busy goes low and before the next eoc, I can see the reads of two channels. But your picture helped a lot. 

 

Thank you, 

Benaka

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