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Contributor
Contributor
342 Views
Registered: ‎09-13-2016

XC7Z045 drive strength

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Hi,

I wonder what the drive strength of this pin is in XC7Z045..Also, what is output impedance? where can I find related info?

set_property IOSTANDARD LVCMOS33 [get_ports PIN_A]
set_property PACKAGE_PIN N26 [get_ports PIN_A]

 

Thanks,

J

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1 Solution

Accepted Solutions
311 Views
Registered: ‎01-22-2015

Re: XC7Z045 drive strength

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@centaros 

From Xilinx document UG865 we find that pin N26 of the XC7Z045-FFG900 is in bank-13, which is an HR bank.

Table 1-8 in UG471 shows that HR banks support the LVCMOS33 standard with drive strengths of 4, 8, 12, 16, or 24 mA.  You can set the drive strength using the following XDC constraint.

 set_property DRIVE 16 [get_ports PIN_A];  #set drive to 16mA

Table 11 in document, DS191, gives DC input and output levels for LVCMOS33.

We don’t usually worry about impedance when using LVCMOS.  If controlled impedance is important to you, then check out the controled impedance IO standards described in UG471.

Cheers,
Mark

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1 Reply
312 Views
Registered: ‎01-22-2015

Re: XC7Z045 drive strength

Jump to solution

@centaros 

From Xilinx document UG865 we find that pin N26 of the XC7Z045-FFG900 is in bank-13, which is an HR bank.

Table 1-8 in UG471 shows that HR banks support the LVCMOS33 standard with drive strengths of 4, 8, 12, 16, or 24 mA.  You can set the drive strength using the following XDC constraint.

 set_property DRIVE 16 [get_ports PIN_A];  #set drive to 16mA

Table 11 in document, DS191, gives DC input and output levels for LVCMOS33.

We don’t usually worry about impedance when using LVCMOS.  If controlled impedance is important to you, then check out the controled impedance IO standards described in UG471.

Cheers,
Mark

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