UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
317 Views
Registered: ‎11-13-2018

add controlled jitter to data

Hi,

I am using zynq XC7z00 fpga. I want to generate sequence of bits at one pin. But I want to add jitter to my output data. Is there any way that I can add the known value of jitter and how can I do it?  (I am using vivado and VHDL language).

 

Thanks

0 Kudos
3 Replies
288 Views
Registered: ‎01-08-2012

Re: add controlled jitter to data

  I am using zynq XC7z00 fpga.

Perhaps you meant a part number such as XC7Z020?

  I want to generate sequence of bits at one pin. But I want to add jitter to my output data. Is there any way that I can add the known value of jitter and how can I do it? 

How you would do this is determined by the bit rate as well as the characteristics of the jitter.  You won't get a meaningful answer without giving some hints about what you are doing.

  • What is the bit rate?
  • Is the jitter waveform sinusoidal (i.e. single tone) or is it a noise signal?
  • What is the jitter amplitude?  What is the jitter frequency range?
  • Is this a standard interface (e.g. DDR4, 10G Ethernet, E1/T1)?  Do standards apply? (If so, which ones?)

I've designed a few jitter generators (I mean deliberately, as opposed to inadvertent ones that come from passing a clock through an FPGA) over the last few decades.  There are a few different architectures that can be used.

0 Kudos
279 Views
Registered: ‎11-13-2018

Re: add controlled jitter to data

Hi,

Thanks for your response. Yes, I am using XC7Z0070.

  • What is the bit rate?    

           I am using 1MHz clock, so it will be max 1Mbps

  • Is the jitter waveform sinusoidal (i.e. single tone) or is it a noise signal?

        It can be anything. I just want to inject known value of jitter in my data. I think single tone jitter waveform will simplify this.

  • What is the jitter amplitude?  What is the jitter frequency range?

          Jitter amplitude should be max 100mV and frequency would be 1MHz.

  • Is this a standard interface (e.g. DDR4, 10G Ethernet, E1/T1)?  Do standards apply? (If so, which ones?)

     No specific standard. I just sending sequence of bits from fpga and plotting eye diagram on scope. I want to deliberately add jitter             and    want to see how much injected jitter closes the eye-diagram.

I hope you get an idea what I am looking for! Thanks my friend.

0 Kudos
272 Views
Registered: ‎01-08-2012

Re: add controlled jitter to data

I think we have a terminology problem here.  When I talk about jitter, I mean the sequence of time differences between when a (nominally) periodic event (e.g. a clock edge) actually happened and when it was ideally supposed to happen.  There are some other definitions (e.g. cycle to cycle jitter) but in all cases they are related to an error in timing.  Here's an introductory article.

So when you say the jitter amplitude should be a voltage (rather than a time), I think you are talking about something other than the usual definition(s) of jitter.  Possibly you mean "all the impairments that might cause the eye to close" in which case timing jitter is a part of that.

 

In terms of actually solving your problem, 1Mb/s is quite slow.  This allows you to use a phase accumulator to generate the jittered 1MHz clock that clocks out the jittered data.  It will do that by dividing down some higher frequency (hundreds of MHz) reference clock down to the 1MHz you need.  You can use another phase accumulator with sinusoidal output to either phase modulate or frequency modulate the first phase accumulator to control the jitter.  I guess from your username that you are a student, so hopefully you should have enough "signals and systems" by now to be able to convert freely between sinusoidal phase modulation, frequency modulation and jitter.

You can use a regular I/O pin for the data at these rates.

To see the eye on an oscilloscope requires a triggering signal.  This will either come from a CDR that recovers the clock from the stream of data bits OR it will come from an unjittered 1MHz clock out of your FPGA.  In your case the latter way will be much easier, and you can use yet another phase accumulator to generate the triggering signal on another output pin.

0 Kudos