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11,166 Views
Registered: ‎03-25-2016

axi quad spi slave mode maximum sck frequency

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Dear all,

 

I’m using axi_quad_spi to implement a slave SPI device on xc7a75tftg256-3.

 

axi_quad_spi is configured in Legacy mode ( using AXI_LITE / axi_aclk 156.25 Mhz  ) 

the pins used to connect with external Master device are :

       io0_i : MOSI

       io0_o : MISO

       sck_i : input master clock

       spisel : slave select

 

The only pin left that I have to connect is  the ext_spi_clk . I referred to AXI Quad SPI v3.2 LogiCORE IP Product Guide document to understand its functionality but stills ambiguous.

 

This is what I found in the doc:

 

    - (Page 83) there are two clock modes:

                                  1. Asynchronous, the ext_spi_clk and the axi clock differ in terms of phase/polarity and frequency

                                  2. Synchronous the ext_spi_clk and the axi clock are equal.

 

    - (Page 82) the spi working clock frequency is obtained by dividing the ext_spi_clk   by the frequency ratio.

 

    - (Page 53) when configured in spi slave mode to ensure proper operations the frequency ratio must be greater than 4 when working in asynchronous mode, and can be equal to 4 in synchronous mode.

 

    - (page 18) table 2-1 shows the maximum frequencies for the AXI Quad SPI core.

For artix -7 (-3): max AXI freq = 160 Mhz and max freq on ext_spi_clk = 80 Mhz. (it seems to be for asynchronous mode?).

 

    - (page 21) note 1 says: AXI clock is expected to be faster than ext_spi_clk.

Which is not true for synchronous mode !! 

 

After highlighting those points found in the document here are my questions:

 

in synchronous mode  ( axi_clock = ext_spi_clk  ) can i have ext_spi_clk  = axi_clock = 156.25 MHz ?? ( I tested this configuration and after implementation the timing requirement were satisfied )

 

What is the best configuration to get the maximum spi slave frequency?

 

If we consider that the ext_spi_clk   max freq is equal to 80 MHz then the maximum slave frequency is 80 / 8(freq ratio) = 10 MHz

Is this true?

 

I'm a beginner and I need your help,

Thanks 

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1 Solution

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8,488 Views
Registered: ‎03-25-2016

Re: axi quad spi slave mode maximum sck frequency

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Finally i used the followed configuration and it works fine 

 

ext_spi_clk   = 80 MHz

freq ratio = 8

 

so the SPI clock is 10 MHz.

 

I don't know if it is the maximum slave frequency for the xc7a75tftg256-2.

 

Best regards.

 

 

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Xilinx Employee
Xilinx Employee
10,105 Views
Registered: ‎08-01-2012

Which version of Xilinx tools are you using? Based on too...

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Which version of Xilinx tools are you using? Based on tools version please check whether any of the below answer record information is helpful to give some debug clues?

http://www.xilinx.com/support/answers/64238.html

http://www.xilinx.com/support/answers/58291.html

http://www.xilinx.com/support/answers/54408.html

http://www.xilinx.com/support/answers/64257.html

 

FYI: Below are some other useful documentation in relation with xi quad spi

  • (PG153) LogiCORE IP AXI Quad Serial Peripheral Interface (SPI) PG100 LogiCORE IP AXI External Memory Controller (EMC)
  • XAPP1176 Using Execute-in-Place (XIP) with AXI Quad SPI in Vivado IP Integrator
  • XAPP797 Throughput Performance Measurements for AXI Quad SPI IP Core (7 series)

 

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

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8,489 Views
Registered: ‎03-25-2016

Re: axi quad spi slave mode maximum sck frequency

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Finally i used the followed configuration and it works fine 

 

ext_spi_clk   = 80 MHz

freq ratio = 8

 

so the SPI clock is 10 MHz.

 

I don't know if it is the maximum slave frequency for the xc7a75tftg256-2.

 

Best regards.

 

 

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Visitor cantabria
Visitor
4,527 Views
Registered: ‎03-14-2017

Re: axi quad spi slave mode maximum sck frequency

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I have a problem with the AXI Quad SPI v3.2 as slave mode. I want to use with several frequencies of SPI Master, like 1 Mhz and 20 Mhz. In the hardware system, which frequency has to be in the ext_spi_clock pin?  The s_axi4_aclk is 100Mhz.

 

SW -> Vivado 2016.4.

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4,322 Views
Registered: ‎03-25-2016

Re: axi quad spi slave mode maximum sck frequency

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Hi 

 

What family are you using ARTIX-7, KINTEX-7 or VIRTEX-7 ? And what is the speed grade of your FPGA part ?

According to that you can get the spi slave maximum frequency using the table table 2-1 (page 18) of the IP documentation

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf

 

 

Best regards,

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