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Voyager
Voyager
81 Views
Registered: ‎08-16-2018

can I drive an LVDS device from DIFF_SSTL15?

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I have an Artix-7 and have only an HR bank powered at 1V5 available to send some clock to another IC with LVDS input.

From the 7-series datasheet, DIFF_SSTL is:

Untitled picture.png

which is fine for a VICM = 1V5/2 = 0V75 and VID = 0V375. My worry is the swing voltage in the table above is minimum, and VID could be greater than that, potentially exceeding the input specs... is there any spec for VOL (min) and VOH (max)? for 7-series?

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1 Solution

Accepted Solutions
51 Views
Registered: ‎01-22-2015

Re: can I drive an LVDS device from DIFF_SSTL15?

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Hi John,

I can't find a definite answer to your questions - but we can perhaps infer some things from Fig 1-59 in UG471.  That is, with the 50-ohm pullup to 0.75V, each line of the DIFF_SSTL15 output cannot range outside of 0.25V-to-1.25V - otherwise the FPGA pin will be sinking/sourcing more the 10mA allowed for 7-Series.

Also, if you're planning to use the typical 100-ohm termination at the LVDS receiver, check that this will not cause the DIFF_SSTL15 pins to sink/source more than 10mA.

Hopefully someone from Xilinx will give us some guidance.

Mark

2 Replies
52 Views
Registered: ‎01-22-2015

Re: can I drive an LVDS device from DIFF_SSTL15?

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Hi John,

I can't find a definite answer to your questions - but we can perhaps infer some things from Fig 1-59 in UG471.  That is, with the 50-ohm pullup to 0.75V, each line of the DIFF_SSTL15 output cannot range outside of 0.25V-to-1.25V - otherwise the FPGA pin will be sinking/sourcing more the 10mA allowed for 7-Series.

Also, if you're planning to use the typical 100-ohm termination at the LVDS receiver, check that this will not cause the DIFF_SSTL15 pins to sink/source more than 10mA.

Hopefully someone from Xilinx will give us some guidance.

Mark

Voyager
Voyager
32 Views
Registered: ‎08-16-2018

Re: can I drive an LVDS device from DIFF_SSTL15?

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This
"That is, with the 50-ohm pullup to 0.75V, each line of the DIFF_SSTL15 output cannot range outside of 0.25V-to-1.25V - otherwise the FPGA pin will be sinking/sourcing more the 10mA allowed for 7-Series"
and
"Also, if you're planning to use the typical 100-ohm termination at the LVDS receiver, check that this will not cause the DIFF_SSTL15 pins to sink/source more than 10mA"

are kind of incompatible... if the first is true, there is no problem with the second, the limited current will limit the voltage.

But the principle is valid. It's all down to whether the current is limited by the device (and I believe it is)

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