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Visitor amb5l
Visitor
404 Views
Registered: ‎08-29-2018

fast inversion and distribution of a slow external clock

Hi all,

 

I need to invert an external clock and distribute globally, with minimum delay, in my 7-series design. The clock is too slow (1 MHz) for DLLs/PLLs. I have no specific delay target but the faster the better.

 

I have started with this: clock capable pin -> IBUFG -> LUT inverter -> BUFG -> global clock.

 

Is there a better way?

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2 Replies
Scholar drjohnsmith
Scholar
388 Views
Registered: ‎07-09-2009

Re: fast inversion and distribution of a slow external clock

You have an interesting problem there,

 

not certain you can route through  a lut to the global clock without considerable / variable delay.

 

Can you cope with jitter ?

 

you could treat the 1 mhz clock as a signal, 

   sample it to a much faster internal clock, say 200 MHz,

        observer all the normal clock crossing issues, but generate a single 200 Mhz pulse off the rising edge of the 1 MHz.

              you will have 5ns jitter on this, but the delay will be small and predictable.

 

 

Visitor amb5l
Visitor
377 Views
Registered: ‎08-29-2018

Re: fast inversion and distribution of a slow external clock

Good idea.

 

I need to latch an external data bus that is synchronous to the slow external clock - on the falling edge of course... My recipe for this will be: clock capable pin -> IBUFG -> BUFIO -> IDDR in OPPOSITE_EDGE mode (using Q2 output only). I will then work on the data and do everything else in a 100 MHz domain, having double sychronised the slow external clock and detected its falling edges.

 

Thankyou!

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