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Participant sythez
Participant
6,018 Views
Registered: ‎03-22-2011

flip-flops defect in specific clock region

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Hi, I am using Kintex7 410t (ffg900) and need some help about test result seems to be hardware defect.

 

I configured FPGA with FF test module as below (brief code) and found CLOCK_REGION_X0Y3 ~ X1Y3 is not operating.

 

The output of FF test module, logic ANDed bit of (so many) counters which is assigned to each clock region, is connected to test pins, so I can recognize which region is operating properly or not. (with oscilloscope)

 

IO pin in that bank, 15, is operating well.

 

question is :

 

Q1 : Is it possible that FFs in specific clock region are operating improperly without any defect?

 

Q2 : If the FFs is broken(failure, defect, whatever), why does it occur? ( ESD, circuit design error ..?)

 

 

I have 3 FPGA boards that FFs in clock region X0Y3-X1Y3 is not operating properly. (among 30 good boards)

 

 

 

 

 

brief code of FF test

 

create_pblock pblock_1
add_cells_to_pblock [get_pblocks pblock_1] [get_cells -quiet [list TEST_SLICE_A/TEST_SLICE_Z00 TEST_SLICE_A/TEST_SLICE_Z04 TEST_SLICE_A/TEST_SLICE_Z08 TEST_SLICE_A/TEST_SLICE_Z12 TEST_SLICE_A/TEST_SLICE_Z16 TEST_SLICE_A/TEST_SLICE_Z20 TEST_SLICE_A/TEST_SLICE_Z24 TEST_SLICE_A/TEST_SLICE_Z28]]
resize_pblock [get_pblocks pblock_1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X1Y0}

...

 

 


TEST_SLICE_Z #(.DATA_WIDTH(DATA_WIDTH- 0), .TAP(TAP), .CNT_NN(1)) TEST_SLICE_Z00(nReset, clk, out_led00 );
TEST_SLICE_Z #(.DATA_WIDTH(DATA_WIDTH- 1), .TAP(TAP), .CNT_NN(1)) TEST_SLICE_Z01(nReset, clk, out_led01 );
TEST_SLICE_Z #(.DATA_WIDTH(DATA_WIDTH- 2), .TAP(TAP), .CNT_NN(1)) TEST_SLICE_Z02(nReset, clk, out_led02 );

...

 

assign out_led[0] = {~(out_led00 & out_led04 & out_led08 & out_led12 & out_led16 & out_led20 & out_led24 & out_led28)};
assign out_led[1] = {~(out_led01 & out_led05 & out_led09 & out_led13 & out_led17 & out_led21 & out_led25 & out_led29)};
assign out_led[2] = {~(out_led02 & out_led06 & out_led10 & out_led14 & out_led18 & out_led22 & out_led26 & out_led30)};
assign out_led[3] = {~(out_led03 & out_led07 & out_led11 & out_led15 & out_led19 & out_led23 & out_led27 & out_led31)};

 

module TEST_SLICE_Z(nReset, clk, out_led );

parameter CNT_NN=16;
parameter DATA_WIDTH=256;
parameter TAP=25;

input nReset;
input clk;
output out_led;

wire [CNT_NN-1:0] out_led00, out_led01, out_led02, out_led03, out_led04;
wire [CNT_NN-1:0] out_led05, out_led06, out_led07, out_led08, out_led09;

 

...

 

genvar ch;
generate
for (ch=0;ch<CNT_NN;ch=ch+1)
begin : gen_led_test0
TEST_SLICE #(.DATA_WIDTH(DATA_WIDTH-00), .TAP(TAP)) TEST_SLICE00 (nReset, clk, out_led00[ch]);
TEST_SLICE #(.DATA_WIDTH(DATA_WIDTH-01), .TAP(TAP)) TEST_SLICE01 (nReset, clk, out_led01[ch]);
TEST_SLICE #(.DATA_WIDTH(DATA_WIDTH-02), .TAP(TAP)) TEST_SLICE02 (nReset, clk, out_led02[ch]);

...

 

 

module TEST_SLICE(nReset, clk, out_led );

parameter DATA_WIDTH=26;
parameter TAP=25;

input nReset;
input clk;
output out_led;


reg [DATA_WIDTH-1:0] TEST_CNT00, TEST_CNT01, TEST_CNT02, TEST_CNT03, TEST_CNT04;
reg [DATA_WIDTH-1:0] TEST_CNT05, TEST_CNT06, TEST_CNT07, TEST_CNT08, TEST_CNT09;

...

 

always@(posedge clk or negedge nReset)
begin
if(~nReset) begin
TEST_CNT00 <= 0;
TEST_CNT01 <= 0;
TEST_CNT02 <= 0;
...

end
else begin
TEST_CNT00 <= TEST_CNT00 + 1'b1;
TEST_CNT01 <= TEST_CNT01 + 1'b1;
TEST_CNT02 <= TEST_CNT02 + 1'b1;
...
end
end

 

always@(posedge clk or negedge nReset)
begin
if(~nReset) begin
test_led0 <= 0;
test_led1 <= 0;
test_led2 <= 0;
test_led3 <= 0;
end
else begin
test_led0 <= {TEST_CNT00[TAP]&TEST_CNT01[TAP]&TEST_CNT02[TAP]&TEST_CNT03[TAP]&TEST_CNT04[TAP]&TEST_CNT05[TAP]&TEST_CNT06[TAP]&TEST_CNT07[TAP]&TEST_CNT08[TAP]&TEST_CNT09[TAP]};
...

end
end


reg out_led;
always@(posedge clk or negedge nReset)
begin
if(~nReset) begin
out_led <= 0;
end
else begin
out_led <= test_led0 & test_led1 & test_led2 & test_led3;
end
end

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1 Solution

Accepted Solutions
Scholar austin
Scholar
11,208 Views
Registered: ‎02-27-2008

Re: flip-flops defect in specific clock region

Jump to solution

s,

 

Out of the hundreds of thousands of CLB DFF, suddenly three exactly the same ones go bad on three boards?

 

Unless you have removed the heat spreader, and attacked them with a laser or FIB, it remains as unlikely a scenario as I could possibly imagine.  You could arrange to return them through your distributor on a RMA, but it is extremely likely (not impossible) that upon testing, they will be 'no problem found.'

 

No emotion here, I am just offering you my opinion after all my years in the industry.

 

Last idea:  if these are physically located in the IOB, or immediately adjacent to an IOB, then ESD to the same pin may have destroyed the same area in three devices.  Never heard of adjacent cell damage being identical, but maybe there are many others destroyed, as well.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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6 Replies
Scholar austin
Scholar
5,989 Views
Registered: ‎02-27-2008

Re: flip-flops defect in specific clock region

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s,

 

Sure sounds like some serious miss-handling (ESD).  But, three boards broken exactly the same way?  Not likely!

 

So, I suspect your test is at fault (there is nothing wrong with anything.

 

And, the probability of three parts bad at shipment the same way is also zero.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant sythez
Participant
5,971 Views
Registered: ‎03-22-2011

Re: flip-flops defect in specific clock region

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Hi Austin, thank you for your reply.

 

the three board is working fine at first.

 

the board for signal processing has some registers which can be read/write with DSP address/data bus.

 

the registers have worked fine at first, but now, it is not.

 

so I made some test module for verify FF's operation :

1. there are many counters(using over 90%)and output the result of ANDing the MSB of counters

2. area constraint for matching counters and clock region.

 

the outputs of my test module is connected to LEDs and test point on the board,

 

the led connected clock region x0y3-x1y3 is not blinking.

 

other LEDs and signals on test point are blinking.

 

I got same result, clock region x0y3-x1y3  , when I change the area constraint (pblock) and connected LEDs.

 

so I think my test is not at fault. also, there is no timing error at vivado.

 

I think shipment is not the source of problem, same as your opinion.

 

 

 

I want to know that if there is anything possible to damage the specific clock region or FFs.

 

 

Best Regards,

Sythez

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Scholar austin
Scholar
5,955 Views
Registered: ‎02-27-2008

Re: flip-flops defect in specific clock region

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s,

 

Three devices with exactly the same failure?

 

Impossible.

 

Something else is happening you have not discovered (bad LED?).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant sythez
Participant
5,942 Views
Registered: ‎03-22-2011

Re: flip-flops defect in specific clock region

Jump to solution

Hi Austin,

 

As the result of my test, three are the same. bad LED? :)

 

I have no intention to blame or annoying anyone, but I am sorry if you feel so.

 

However, I can not understand your conclusion, 'Impossible'

 

there must be some point to review or check, (circuit design, pcb pattern or etc..) that is the point I want to know but you said only impossible, nothing wrong with anything, fault test. (perhaps, is my case the first case in world-wide? OMG! )

 

i am very disappointed how to handle the client's question.

 

 

 

Best Regards,

 

0 Kudos
Scholar austin
Scholar
11,209 Views
Registered: ‎02-27-2008

Re: flip-flops defect in specific clock region

Jump to solution

s,

 

Out of the hundreds of thousands of CLB DFF, suddenly three exactly the same ones go bad on three boards?

 

Unless you have removed the heat spreader, and attacked them with a laser or FIB, it remains as unlikely a scenario as I could possibly imagine.  You could arrange to return them through your distributor on a RMA, but it is extremely likely (not impossible) that upon testing, they will be 'no problem found.'

 

No emotion here, I am just offering you my opinion after all my years in the industry.

 

Last idea:  if these are physically located in the IOB, or immediately adjacent to an IOB, then ESD to the same pin may have destroyed the same area in three devices.  Never heard of adjacent cell damage being identical, but maybe there are many others destroyed, as well.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant sythez
Participant
5,915 Views
Registered: ‎03-22-2011

Re: flip-flops defect in specific clock region

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Hi Austin

 

Thank you for your reply and , as you suggested, I will contact our distributor how to use RMA service. 

 

I will inform you of this result.

 

Thank you again for your help :)

 

 

Best Regards,

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