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Adventurer
Adventurer
6,515 Views
Registered: ‎06-27-2016

iodelay_group cells have been found but have no idelayctrl associated with it

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Hi,

I am trying to integrate 1G trimode ethernet  example design with 10G ethernet example design ,both sharing same 200 MHz clk.

While place_design it is giving [DRC 23-20] voilation(PLIDC -1)IDELAYCTRL missing, i tried to put all iodelays in one p bock along with a idelayctrl but it ani't working.

Any solution?

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Xilinx Employee
Xilinx Employee
11,777 Views
Registered: ‎09-20-2012

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi

 

 

Include the below constraint in top level XDC and rerun the synthesis and implementation

 

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells V7IO_BD_i/axi_ethernet_0_example_0/inst/axi_ethernet_0_support/axi_ethernet_idelay_ctrl]

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
6,509 Views
Registered: ‎09-20-2012

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi

 

Please post the complete error message.

Thanks,
Deepika.
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Adventurer
Adventurer
6,492 Views
Registered: ‎06-27-2016

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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[DRC 23-20] Rule violation (PLIDC-1) IDELAYCTRL missing from group with assigned IODELAYs - IODELAY cells have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp', but there is no IDELAYCTRL associated with this IODELAY_GROUP.

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Adventurer
Adventurer
6,480 Views
Registered: ‎06-27-2016

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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I tried to search 'tri_mode_ethernet_mac_iodelay_grp' in files but could not find it, even if i try to instantiate a idelayctrl primitive got no clue how to map and group it to this iodelay group.
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Xilinx Employee
Xilinx Employee
6,476 Views
Registered: ‎09-20-2012

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi

 

While generating the IP, did you choose "shared logic in core" or shared logic in example design"?

 

Can you open synthesized design and search for cells for type "IDELAYCTRL" using below command? 

 

show_objects -name find_1 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IDELAYCTRL.IDELAYCTRL } ]

 

If possible upload the _opt.dcp file located in .runs-->impl_1 folder.

Thanks,
Deepika.
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Adventurer
Adventurer
6,469 Views
Registered: ‎06-27-2016

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Ip is generated  with 'Include shared logic in example design' .

Yes a idelay_ctrl is in nets under axi_ethernet nets.

 

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Xilinx Employee
Xilinx Employee
6,466 Views
Registered: ‎09-20-2012

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi

 

Can you check the IODELAY_GROUP property of the IDELAYCTRL instance?

 

Also upload the _opt.dcp file located in .runs-->impl_1 folder

Thanks,
Deepika.
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Adventurer
Adventurer
6,458 Views
Registered: ‎06-27-2016

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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These constraint i found in the example design and commented them then packaged the design as ip.

<<  # Group IODELAY components
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells {rgmii_interface/delay_rgmii_tx* rgmii_interface/txdata_out_bus[*].delay_rgmii_tx*}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells {rgmii_interface/delay_rgmii_rx* rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]  >>

 

Below is the idelayctrl inst in the example design and find the attached .dcp file.

IDELAYCTRL #(
.SIM_DEVICE ( "7SERIES" )
) axi_ethernet_idelay_ctrl
(
.RDY (idelayctrl_ready),
.REFCLK (ref_clk ),
.RST (idelayctrl_reset)
);

axi_ethernet_0_support_resets axi_ethernet_support_resets
(
.idelayctrl_ready (idelayctrl_ready ),
.idelayctrl_reset_out (idelayctrl_reset ),
.ref_clk (ref_clk ),
.resetn (s_axi_lite_resetn)
);

 

I also tried to give two different clk@200Mhz to both 10G and 1G but still same placement error.

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Xilinx Employee
Xilinx Employee
11,778 Views
Registered: ‎09-20-2012

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi

 

 

Include the below constraint in top level XDC and rerun the synthesis and implementation

 

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells V7IO_BD_i/axi_ethernet_0_example_0/inst/axi_ethernet_0_support/axi_ethernet_idelay_ctrl]

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Adventurer
Adventurer
6,437 Views
Registered: ‎06-27-2016

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Thank-You for your answer it resolved the issue. Any document to refer in future for such issues?
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Moderator
Moderator
3,753 Views
Registered: ‎07-01-2015

Re: iodelay_group cells have been found but have no idelayctrl associated with it

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Hi @yogesh_tripathi,

 

Please go through https://www.xilinx.com/support/answers/52502.html and https://www.xilinx.com/support/answers/59774.html

 

 

Thanks,
Arpan
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