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Visitor yfp303
Visitor
5,228 Views
Registered: ‎10-10-2012

pin delay inside K7 FFG900 package

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Now I need to estimate the whole line delay on PCB. It's better to know the pin delay   inside K7  FFG900 package.But,I just    can't  find  anything about it .Anybody can tell me which kind of file defines pin delay.Thank you!

 

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Xilinx Employee
Xilinx Employee
6,661 Views
Registered: ‎08-02-2007

Re: pin delay inside K7 FFG900 package

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In Vivado you can export IO and the resulting csv has delay in ps.  Also Partgen -v <PART>  from a command line exports a text file .pkg that also gives delay in time.

 

Regards,

Jon

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Xilinx Employee
Xilinx Employee
6,662 Views
Registered: ‎08-02-2007

Re: pin delay inside K7 FFG900 package

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In Vivado you can export IO and the resulting csv has delay in ps.  Also Partgen -v <PART>  from a command line exports a text file .pkg that also gives delay in time.

 

Regards,

Jon

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5,195 Views
Registered: ‎02-20-2008

Re: pin delay inside K7 FFG900 package

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Is it possible to get partgen report with trace lengths for 7-Series packages? 

 

PCB designers claim that report with lengths in "um" (for previous families) was more convenient than delays.

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Xilinx Employee
Xilinx Employee
5,186 Views
Registered: ‎08-02-2007

Re: pin delay inside K7 FFG900 package

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7 series should be in ps.

 

-Jon

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