UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
168 Views
Registered: ‎12-16-2010

placement of BUFIO2 non-inverting / inverting on Spartan6 LX100

Hello,

I'm developing a product based on Spartan6 LX100, employing several clocks.

On bank3 are connected three RGMII interfaces (TX and RX channels with separated clocks running at 125 MHz and operating in DDR mode), clocks and related signals are carefully placed to the same half bank.

These interfaces are named RGMII_CPU (TX and RX bank3 bottom), RGMII_PHY0 (TX and RX on bank 3 top) and RGMII_PHY1 (TX and RX on bank 3 top).

On bank3 bottom are connected other signals for a synchronous bus interface operating in SDR mode.

For completeness, on bank2 is present another LVDS clock going to a PLL.

The RGMII TX channels are outputs at the same frequency, so I choosed to use a single clock for all of them, generated with a PLL starting from an external reference. Using a BUFPLL the clock can be propagated on the whole bank 3, covering the three interfaces. The clock structure and data output is implemented as follows:

(25 MHz reference on GCLK26) -> BUFIO2_X1_Y9 -> PLL (CLK0 = 250 MHz, CLK1=125MHz) -> BUFPLL -> OSERDES2 (SDR, serdes factor = 2)

The RGMII RX channels have separated clocks operating in DDR mode, so a pair of BUFIO2 (INVERT=FALSE / INVERT=TRUE) is required to supply clock to IDDR2 inputs. All signals are on the same half-bank of relevant clock input. Please note that the UG382 clocking user guide doesn't report any information about the internal connection of BUFIO2 for bank3, only for bank0 the information is clearly specified in figure 1-7. I assumed that the non-inverted/inverted pairs of BUFIO2 are adjacent as for bank0. The clock structures and data inputs for each RX channel are implemented as follows:

(RX CPU on GCLK24) -> BUFIO2_X1Y15 (INVERT=FALSE) + BUFIO2_X1Y14 (INVERT=TRUE) -> IDDR2 + BUFGMUX_X3Y13

(RX PHY0 on GCLK22) -> BUFIO2_X0Y17 (INVERT=FALSE) + BUFIO2_X0Y16 (INVERT=TRUE) -> IDDR2 + BUFGMUX_X3Y14

(RX PHY1 on GCLK20) -> BUFIO2_X0Y23 (INVERT=FALSE) + BUFIO2_X0Y22 (INVERT=TRUE) -> IDDR2 + BUFGMUX_X3Y16

About other clock present on bank2 and bank3:

(BUS CLOCK on GCLK27) -> BUFIO2_X1Y8 -> BUFGMUX_X2Y9

(LVDS CLOCK on GCLK31) -> BUFIO2_X1Y0 -> BUFGMUX_X2Y12

The complete clock structure of bank2 and bank3 are drawed on attached picture (green BUFIO2 are non-inverting, purple are inverting).FPGA_clock_bank2_bank3.png

Now, I think this structure should work, however Map gives me a lot of unroutable errors and is trying to place BUFIO2 pairs splitted on two different half-banks, but obviously it doesn't works in this way. 

There's somethig wrong in my idea?

 

Thanks

Andrea

 

 

0 Kudos
1 Reply
Adventurer
Adventurer
108 Views
Registered: ‎12-16-2010

Re: placement of BUFIO2 non-inverting / inverting on Spartan6 LX100

Hello,

maybe a Xilinx Expert could help me with the placement of paired inverting/non-inverting BUFIO2 of bank 3?

What is the internal route of the clock from PAD to BUFIO2 for bank3?

Thanks

Andrea

0 Kudos