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Visitor wuzhi
Visitor
9,144 Views
Registered: ‎05-17-2014

2 *1 pcie ep on a GTX_DUAL?

I need to implement two pcie endpoint (width = 1) on a single GTX_DUAL, using Virtex-5 FX70T.

But now the problem is  that Coregen generates a pcie ep with a GTX_DUAL.

And I have tried to generate two pcie ep (primary ep & secondary ep), and modify the code to implement one GTX_DUAL in the primary ep part. However, it does not work, cause host can only see one pcie endpoint.

 

Can a GTX_DUAL distribute to two pcie ep?

 

Thanks

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3 Replies
Xilinx Employee
Xilinx Employee
9,118 Views
Registered: ‎07-23-2012

Re: 2 *1 pcie ep on a GTX_DUAL?

Hi,

You can implement two PCIE cores in a GTX_DUAL that shouldn't be a problem.

Regards,
Krishna
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Xilinx Employee
Xilinx Employee
9,114 Views
Registered: ‎08-02-2007

Re: 2 *1 pcie ep on a GTX_DUAL?

You will need to check the ucf file and modify the GT location as needed

 

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Scholar kotir
Scholar
9,107 Views
Registered: ‎02-03-2010

Re: 2 *1 pcie ep on a GTX_DUAL?

Hi,

 

Check thefile <generated core location>/ pcie_gtx_wrapper.v/vhd.

 

There are generate and end generate statements for the implementation of DUAL tile for the usage of which channel to be used.

By default the code occupies the Channel0 of the DUAL time.

 

You need to modify this for one of the core you want to imeplement for Channel1.

 

For example

Change the following

              .RXVALID0(gt_rx_valid_reg[i+0]),

              .RXVALID1(gt_rx_valid_reg[i+1]),

to

              .RXVALID0(gt_rx_valid_reg[i+1]),

              .RXVALID1(gt_rx_valid_reg[i+0]),

 

This applies to all the signals of the instance.

Then the tile1 gets connected to the PCIe block instead of tile 0.

 

So this way you can take the data from the lower channel to PCIe_0 instance and data from Upper channel to PCIe_1 instance.

 

Check if you way you can implement twi instances in one DUAL tile.

 

Regards,

KR

 

 

 

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