UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
563 Views
Registered: ‎09-07-2014

7-Series PCIe Gen3 Max Payload Size

Jump to solution

Dear Members,

 

I am developing a PCIe Gen3 application in 7-series FPGA (xc7vx690t-2ffg176) and found some inconsistency in the IP documentation

 

1. The product guide (pg023 v4.3 page 8) states that the IP is capable to support a Max Payload Size of up to 1024B.

 

2 .However, in the Completer Completion descriptor fields (pg023 v4.3 page 119), the DWord Count field is defined as

the size of the payload of the current packet in Dwords, and range between 0-1024 DWs, which is more than the Max Payload Size parameter state before.

 

3. Similarly, in the Requester Completion descriptor fields (pg023 v4.3 page 154), the DWord Count field is defined as

the size of the payload of the current packet in Dwords, and range between 0-1024 DWs, which again, is more than the Max Payload Size parameter state before.

 

So, basically, my question is what should be the right definition for these fields?

 

Thanks ahead! 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
466 Views
Registered: ‎02-16-2010

Re: 7-Series PCIe Gen3 Max Payload Size

Jump to solution

@nissan.luzon

It seems I was wrong. Max payload size is limited to 1024bytes. 

 

The range specified in the sections you referred to as saying 1024Dwoards is based on the PCIe spec. The spec allows that a packet can be 1024Dwoards. It is not related to the supported max payload size with V7 Gen3 IP.

If you check Table B-1 on page 297 of PG023 v4.3, you can find Max Payload Size is limited to 1024 bytes.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
4 Replies
Moderator
Moderator
516 Views
Registered: ‎02-16-2010

Re: 7-Series PCIe Gen3 Max Payload Size

Jump to solution
Please check table 2-14, the max payload size with Virtex-7 gen3 IP is 4096bytes. We will fix the page 8 of PG023.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Contributor
Contributor
491 Views
Registered: ‎09-07-2014

Re: 7-Series PCIe Gen3 Max Payload Size

Jump to solution

Hi venkata,

Thank you for your reply. I see now that table and that indeed correlates with the CC and RC description above.

However, if the MaxPayloadSize can optionally be set to 4096B, why I can't configure the Integrated Block GUI with such value? The maximum value presented in the GUI is 1024B, as can be shown in the screen shot below (captured from Vivado 2018.2, but is the same for older versions of the tool):

SnipImage.JPG

 

 

 

 

 

0 Kudos
Moderator
Moderator
467 Views
Registered: ‎02-16-2010

Re: 7-Series PCIe Gen3 Max Payload Size

Jump to solution

@nissan.luzon

It seems I was wrong. Max payload size is limited to 1024bytes. 

 

The range specified in the sections you referred to as saying 1024Dwoards is based on the PCIe spec. The spec allows that a packet can be 1024Dwoards. It is not related to the supported max payload size with V7 Gen3 IP.

If you check Table B-1 on page 297 of PG023 v4.3, you can find Max Payload Size is limited to 1024 bytes.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Highlighted
Contributor
Contributor
446 Views
Registered: ‎09-07-2014

Re: 7-Series PCIe Gen3 Max Payload Size

Jump to solution

OK, that’s seems to solve the issue.

I think Xilinx should update the sections mentioned such they describe the core capabilities rather than the PCIe spec.

Anyway, thank for your help!!

0 Kudos