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Contributor
Contributor
421 Views
Registered: ‎06-12-2018

7 series PCIe Example Design PIO RX Engine

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Hi,

 

I would like to ask about the working principle of PIO RX ENGINE part of the example designs for PCIe Integrated Block.

My configuration is Endpoint device.

 

In order to understand how it works i examined simulation results.

For a 32 bit memory write transaction (from root complex to Endpoint) I used such a stimulate test bench code:

 

--32 bit write transcation request--------------------------------------------------------------------------------------------
m_axis_rx_tdata <= x"0000000f_40000001";    --TLP Header 0 and TLP Header 1
m_axis_rx_tvalid <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tdata <= x"11223344_80000000"; -- TLP Header 3 ( Adress)  and 32 bit TLP Data
m_axis_rx_tlast <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tvalid <= '0';
m_axis_rx_tlast <= '0';

 

It works fine and data x11223344 is written to x80000000 adress correctly.

 

Problem is that it does not work for back to back two write transactions. The second transaction is lost.

 

Example test bench:

 

--32 bit write transcation request back to back----------------------------------------------------------------------------------------
m_axis_rx_tdata <= x"0000000f_40000001";    --TLP Header 0 and TLP Header 1
m_axis_rx_tvalid <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tdata <= x"11223344_80000000"; -- TLP Header 3 ( Adress)  and 32 bit TLP Data
m_axis_rx_tlast <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tvalid <= '0';
m_axis_rx_tlast <= '0';

 

wait for 1 us;
wait until rising_edge(user_clk);

 

m_axis_rx_tdata <= x"0000000f_40000001";    --TLP Header 0 and TLP Header 1
m_axis_rx_tvalid <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tdata <= x"11223344_80000004"; -- TLP Header 3 ( Adress)  and 32 bit TLP Data
m_axis_rx_tlast <= '1';
wait until rising_edge(user_clk);
m_axis_rx_tvalid <= '0';
m_axis_rx_tlast <= '0';

 

Second transaction is lost and the data x11223344 is not written to x80000004 adress.

 

While i tried to make back to back 4 transactions, 1. and 3. transaction is working but 2. and 4. transactions are lost.

 

I examined the vhdl code of PIO_EX_ENGINE.vhd and i am thinking that this problem is because of the below code parts:

 

-- Create logic to determine when a packet starts
sop <= not (in_packet_q) and m_axis_rx_tvalid;

process
begin
wait until rising_edge(clk);
   if (rst_n = '0') then
       in_packet_q <= '0' after TCQ;
   elsif (m_axis_rx_tvalid = '1' and m_axis_rx_tready_int = '1' and m_axis_rx_tlast = '1') then
       in_packet_q <= '0' after TCQ;
   elsif (sop = '1' and m_axis_rx_tready_int = '1') then
       in_packet_q <= '1' after TCQ;
   end if;
end process;

in_packet_q signal is initally '0' so first transaction is ok. when first transaction starts in_packet_signal is '1'. 

in_packet_q signal does not get '0' value before the second transaction is arrived.

It gets '0' value after the second transaction and so second transaction is lost but third transaction is ok. 

 

 Anyone worked with this example design ?

 

Thanks.

 

Mustafa 

 

 

 

 

 

 

 

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1 Solution

Accepted Solutions
Moderator
Moderator
362 Views
Registered: ‎06-29-2011

Re: 7 series PCIe Example Design PIO RX Engine

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Hi @mustafa.su

 

PIO example design is provided to exercise only basic core functionality. It has very small BRAMs (back-end memory) and will only respond to 1DW payload data (4 Bytes) per packet. Anything larger (or burst) is not supported.

 

Below are some details of the PIO example design:

***************************************************************************************************************************

1. The PIO design is a simple target-only application that interfaces with the Endpoint for PCIe cores Transaction (TRN) interface.
2. The PIO design only supports single DWORD payload Read and Write PCI Express transactions to 32/64 bit address memory spaces and IO space with support for completion TLPs.
3. The example design supports one IO space BAR, one 32-bit Memory space (that cannot be the Expansion ROM space), and one 64-bit Memory space. If these limits are exceeded, only the first space of a given type will be activeaccesses to the other spaces will not result in completions.
4. Each space is implemented with a 2 kB memory. If the corresponding BAR is configured to a wider aperture, accesses beyond the 2 kB limit wrap around and overlap the 2 kB memory space.
5. The PIO design successfully processes single DWORD payload Memory Read and Write TLPs and IO Read and Write TLPs. Memory Read or Memory Write TLPs of lengths larger than one DWORD are not processed correctly by the PIO design; however, the core does accept these TLPs and passes them along to
the PIO design. If the PIO design receives a TLP with a length of greater than 1 DWORD, the TLP is received completely from the core and discarded. No corresponding completion is generated.
6. PIO design handles Memory writes and IO TLP writes in different ways: the PIO design responds to IO writes by generating a Completion Without Data (cpl), a requirement of the PCI Express specification.
7. The PIO_32_TX_ENGINE and PIO_64_TX_ENGINE modules generate completions for received memory and IO read TLPs. The PIO design does not generate outbound read or write requests. However, users can add this functionality to further customize the design.

***************************************************************************************************************************

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth
0 Kudos
1 Reply
Moderator
Moderator
363 Views
Registered: ‎06-29-2011

Re: 7 series PCIe Example Design PIO RX Engine

Jump to solution

Hi @mustafa.su

 

PIO example design is provided to exercise only basic core functionality. It has very small BRAMs (back-end memory) and will only respond to 1DW payload data (4 Bytes) per packet. Anything larger (or burst) is not supported.

 

Below are some details of the PIO example design:

***************************************************************************************************************************

1. The PIO design is a simple target-only application that interfaces with the Endpoint for PCIe cores Transaction (TRN) interface.
2. The PIO design only supports single DWORD payload Read and Write PCI Express transactions to 32/64 bit address memory spaces and IO space with support for completion TLPs.
3. The example design supports one IO space BAR, one 32-bit Memory space (that cannot be the Expansion ROM space), and one 64-bit Memory space. If these limits are exceeded, only the first space of a given type will be activeaccesses to the other spaces will not result in completions.
4. Each space is implemented with a 2 kB memory. If the corresponding BAR is configured to a wider aperture, accesses beyond the 2 kB limit wrap around and overlap the 2 kB memory space.
5. The PIO design successfully processes single DWORD payload Memory Read and Write TLPs and IO Read and Write TLPs. Memory Read or Memory Write TLPs of lengths larger than one DWORD are not processed correctly by the PIO design; however, the core does accept these TLPs and passes them along to
the PIO design. If the PIO design receives a TLP with a length of greater than 1 DWORD, the TLP is received completely from the core and discarded. No corresponding completion is generated.
6. PIO design handles Memory writes and IO TLP writes in different ways: the PIO design responds to IO writes by generating a Completion Without Data (cpl), a requirement of the PCI Express specification.
7. The PIO_32_TX_ENGINE and PIO_64_TX_ENGINE modules generate completions for received memory and IO read TLPs. The PIO design does not generate outbound read or write requests. However, users can add this functionality to further customize the design.

***************************************************************************************************************************

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth
0 Kudos