08-17-2017 06:19 AM
I noticed when the pc boots and during pcie configuration, the Xilinx ip core actually pull the axi ready low during transmission of configuration completion TLP to prevent the user from accessing the transmit axi bus.
Why is this necessary?
Since during config time the PC OS is not even loaded, therefore the user can't really use the bus yet.
In addition, there are many buffers inside the pcie core that the physical layer should manage the transmit flow.
The core shouldn't inactivate the axi transmit bus by setting the axi4_tx_tready signal Low.
Besides, the configuration process is ready between the Root and endpoint pcie physical layer, not the transport layer which is the AXI bus.
08-17-2017 08:43 AM
I'm not following what your intentions are. The PCIE bus likely ties the pcie_user_reset line into the TREADY signals. That reset line stays active until the link has gone through initialization, and reached steady state. This is a good thing. The PCIE bus is in reset - by definition NOT ready. Why would you want the interface to not accurately reflect this state on the bus?
08-17-2017 10:25 AM
Actually the the reset line goes away and then the ready is active then the configuration starts. It is the configuration process that pulls the ready line down.
I wasn't sure the reason why the core pulses this signal every time it response to the root during configuration.
Since the PC is not even up yet during config process, why is the AXI bus being control by the pcie core because the apllication is not even active.
Still learning, Just want to understand a little bit more on the AXI bus
08-17-2017 10:52 AM
Wait - I'm unclear which bus you're actually referring to.
The low-level Xilinx PCIE Endpoint has - depending on whether your talking about 7series (or ultrascale) 2 (or 4) AXIS buses basically containing low-level PCIE TLP packets. These AXIS buses should NOT be ready (TREADY) during PCIE negotiations.
Connecting up at a higher level, there can be an AXI bus. (i.e. A[RW]READY, WREADY, BREADY, RREADY). These will depend on just what sort of IP you're connecting to the low-level Endpoint. I know Xilinx has some IP that does this, but we don't use it (we have our own).
Are you referring to the low-level AXIS TREADY lines or some other AXI bus ready condition? If it's the latter then you'll need to provide more specifics on just what bus you're talking about, and what IP is controlling it / where it is with respect to the PCIE endpoint.
08-18-2017 07:01 AM
I'm r3effering to the AXI bus, this is the user bus for rcv and xmt TLP.
During config, the pcie endpoint control and pulse it as it returns a completion TLP. Every time it response to the Root, it pull the tx_ready low and when done it releases it and this continue until enumeration is completed.
My question is why is this necessary since the user will not touch (actually he can't) this bus until the PC finish booting.