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Adventurer
Adventurer
45 Views
Registered: ‎05-09-2018

Access to CFGDEVCONTROLMAXPAYLOAD

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Hello,

I am using an Artix-7 device for a PCIe Gen2x1 design, and I need access to the CFGDEVCONTROLMAXPAYLOAD[2:0] signals in my design. Is there a way to bring these signals to the top of the Vivado generated IP?

I tried enabling each interface under the Core Interface Parameters tab, but could not find these signals.

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Adventurer
Adventurer
23 Views
Registered: ‎05-09-2018

Re: Access to CFGDEVCONTROLMAXPAYLOAD

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Never mind! I found this information is included in the cfg_dcommand value.

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Adventurer
Adventurer
24 Views
Registered: ‎05-09-2018

Re: Access to CFGDEVCONTROLMAXPAYLOAD

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Never mind! I found this information is included in the cfg_dcommand value.

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