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Adventurer
Adventurer
2,508 Views
Registered: ‎08-10-2017

Accessing BAR0 from PC and FPGA

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While using DMA/Bridge subsystem for PCIe, I selected BAR option.Screenshot from 2018-01-25 21-42-18.png

After loading the device driver xdma.ko into kernel using load_driver.sh, I noticed the following using dmesg

Screenshot from 2018-01-25 21-45-35.png

 I have the following doubts - 

  1. Is 0xffffb012418c0000 the address in host PC and is 0xfe410000 the AXI address of BAR0 ?
  2. This memory is allocated as soon as I execute load_driver.sh. This information is present in the object of struct xdma_dev. But I have to access this memory in a custom C code. How to access the information stored in this object of struct xdma_dev from the C code? Is there any API that provides access to "the object of struct xdma_dev" ?
  3. If 0xfe410000 the AXI address of BAR0, how to access it from FPGA logic ?
  4. How to interpret the fields "Value" and "PCIe to AXI Translation" in the first image ?

 

 

Thank You

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Xilinx Employee
Xilinx Employee
3,240 Views
Registered: ‎05-07-2015

Re: Accessing BAR0 from PC and FPGA

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HI @jagannath

 

reg_rw  shell utility provided the driver can be used to access AXI lite connect register

Here is an example of how to read from the AXI-Lite at a specified offset (0x0000).
$Linux> ./reg_rw  /dev/xdma0_user 0x0000 w
Here is an example of how to write to the AXI-Lite Interface at a specified offset (0x0000) with specific data (0x1234567).
$Linux> ./reg_rw /dev/xdma0_user 0x0000 w 0x123456
 
 
 
Thanks
Bharath
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4 Replies
Xilinx Employee
Xilinx Employee
2,417 Views
Registered: ‎05-07-2015

Re: Accessing BAR0 from PC and FPGA

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Hi @jagannath

Firstly the driver /host machine is not aware of the AXI address space on FPGA side. that is the reason the we have to manually enter the correct PCIE  to AXI translation value.

Coming to your queries:

  1. Is 0xffffb012418c0000 the address in host PC and is 0xfe410000 the AXI address of BAR0 ?
    A) Yes 0xffffb012418c0000   is the physical address assigned in HOST host PC for the requested 16kb address space.
    BUT NO , 0xfe410000 is NOT the AXI address of BAR0 . The  16KB AXI Address space in FPGA for  BAR0 would  be ( 0x0000000000000000, 0x0000000000003FFF)
    So you will have look at the address editor in your vivado design and use the the base address of the AXI peripheral  you want to control.accress via PCIE BAR0 as the "PCIE to AXI translation value"
    Please refer to AR65062 (page 4 and 5) to get  more clarity on how PCIE to AXI translation works.

  2. This memory is allocated as soon as I execute load_driver.sh. This information is present in the object of struct xdma_dev. But I have to access this memory in a custom C code. How to access the information stored in this object of struct xdma_dev from the C code? Is there any API that provides access to "the object of struct xdma_dev" ?
    A) If I understand correctly you are trying to  use /mimic the "dd" command utility used to read/write in special device files in C code.
    Checkout this page which may help you.

  3. If 0xfe410000 the AXI address of BAR0, how to access it from FPGA logic ?
    A) NO it is not.
  4. How to interpret the fields "Value" and "PCIe to AXI Translation" in the first image ?
    A) The field "Value": Uninitialized BAR0 value in the config space that is presented to host machine by the End point at the start of enumeration.
       The first MSB that is tied to zero indicates  to host machine the BAR size requested by the EP.
    so if you request 64 KB : value : FFFF0000
     if you request 32 KB : value : FFFF8000
    if you request 16 KB : value : FFFFC000
    Note: in case  of 64 bit selection: bit 2 of the  BAR0 is set to 1. (indicating 64 bit decoding to host machine) - as per PCIE protocol.

    The  usage  of field "PCIe to AXI Translation": is  the  AXI base address of the AXI peripheral that you need to control via BAR0 .(the user is expected to know  this value /one can get this information from the AXI address editor tab on the Vivado block design ). Go through AR65062 for more clarity on this.

 

Thanks
Bharath
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Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
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Adventurer
Adventurer
2,393 Views
Registered: ‎08-10-2017

Re: Accessing BAR0 from PC and FPGA

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@nagabhar

 

Thanks a lot, Bharath.
You've connected the dots very well, and I understand these concepts better now. I'll look into AR65062 more carefully.

 

I would like to add few more points.

  • I realized that the 16KB AXI Address space in FPGA for  BAR0 ( 0x0000000000000000 - 0x0000000000003FFF), is actually the AXI-Lite address. This means that it is not possible to access this memory from dma_to_device and dma_from_device API provided in the driver (unless we make requisite changes using Address Editor)
  • I connected AXI GPIO (LED) to this AXI-Lite address, as shown below (notice the orange connections)Screenshot from 2018-01-29 14-37-12.png
  • Once the BARs are allocated, I added the following snippet in probe() function in xdma-core.c file.Screenshot from 2018-01-29 14-51-29.png
  • Since there are only 8 LEDs, the pattern 0x34 was illuminated (I could've used iowrite8() alternatively).

 

 

 

To give a little background about my ultimate objective, I'm implementing a hardware accelerator in VC707. From my custom C code, I would like to use these BARs

  • to transfer the parameters required for the accelerator
  • to trigger the accelerator so that it can start its computation. 

 

To perform the above from my custom C code, I need the value stored in lro->bar[0] (from struct xdma_dev *lro). Obviously, a new 64-bit physical address is assigned every time I load the driver (load_driver.sh). And it isn't feasible for me to make this change in my C code manually, every time a new address is assigned. So I have to find a way to communicate this physical address to my C code, as soon as I load the driver into the kernel. I'm looking into kernel space to user space IPC like netlink, message queues etc to perform this communication. 

This is the real motivation behind question 2 of my original post. If the method I'm following is inefficient or if there is a better way to do this, please suggest me where I could start.


I would like to thank you once again for your detailed reply.

 

EDIT : 

 

I realized that I cannot access this address directly from userspace C program using iowrite32().
Please suggest me how I can access this BAR from user space C program.

 

 

Regards

Jagannath

 

 

 

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Xilinx Employee
Xilinx Employee
3,241 Views
Registered: ‎05-07-2015

Re: Accessing BAR0 from PC and FPGA

Jump to solution

HI @jagannath

 

reg_rw  shell utility provided the driver can be used to access AXI lite connect register

Here is an example of how to read from the AXI-Lite at a specified offset (0x0000).
$Linux> ./reg_rw  /dev/xdma0_user 0x0000 w
Here is an example of how to write to the AXI-Lite Interface at a specified offset (0x0000) with specific data (0x1234567).
$Linux> ./reg_rw /dev/xdma0_user 0x0000 w 0x123456
 
 
 
Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Adventurer
Adventurer
2,323 Views
Registered: ‎08-10-2017

Re: Accessing BAR0 from PC and FPGA

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@nagabhar

 

Thank you Bharath

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