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590 Views
Registered: ‎09-25-2013

Artix 7 PCIE Custom Board Issues with REFCLK

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There is quite a bit to tell as we have been working this issue for some time and with many efforts.

 

First, we have a prototype system comprised of a computer module socketed in the manufacturer's carrier board that has a PCIE Gen 2 x4 edge socket. We have connected a Xilinx AC-701 development board by edge to the PCIE. We have developed a PCIE Gen 2 x4 lane 5Gbps based design that functions quite well in this prototype.

 

Our next generation is a custom PCB with the same computer module and socket as the carrier board and with the same Artix 7 FPGA using the same connections, power supplies etc. as the AC701. Basically identical to the first generation with respect to the PCIE and following all of the PCIE guidelines from the computer module manufacture, Xilinx, PCI-sig, etc. in the board layout.

 

Reducing our full HDL system design to just the PCIE implementation with loopback we should be able to run the same bit file on both our AC701 prototype and our custom PCB. On the AC701 based system and during computer module boot we see proper operation. PERST negates, REFCLK is present, locks and the PCIE is recognized. However, on the PCB and during the computer module boot, we see the PERST negated and asserted 4 times. We see the REFCLK lock, then loose lock, then gain lock and then stop, but only during the first PERST negation. The REFCLK is never seen by the FPGA again after being lost during the first negation of PERST. This behavior was observed using Vivado and an ILA.

 

Our fist suspicion was the computer module in context with our new PCB. However when we use a 6 Ghz O-scope to observe the REFCLK at the FPGA via, we see that the REFCLK is indeed present and meets specifications from before the first negation of PERST, through the fourth and until after the final assertion of PERST.

 

So our next suspicion was placement of the FPGA on the PCB. We have two boards and both have the same behavior. We sent one of the boards for Xray and rework on the FPGA placement. This board was received and retested today and found to have no change in behavior.

 

We also have another bit file that consists of no PCIE, but rather just the REFCLK connected to the IBUFDS_GTE2 and the PERST. When this bitfile is used on our AC701 based system we see the REFCLK and the four assertions of the PERST as the computer module attempts to recognize the PCIE. On the custom PCB based system the FPGA (using Vivado and an ILA) never sees the REFCLK at all, yet we can clearly see the REFCLK using the O-scope at the FPGA via.

 

We have spent a great deal of time and money trying to solve this on our own. Please provide some assistance.

 

Please see attachment with ILA snapshots.

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450 Views
Registered: ‎09-25-2013

Re: Artix 7 PCIE Custom Board Issues with REFCLK

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The issue has been resolved. The custom board was missing the AC decoupling capacitor on REFCLK.

3 Replies
510 Views
Registered: ‎09-25-2013

Re: Artix 7 PCIE Custom Board Issues with REFCLK

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With no suggestions to this post and no solution found on our end I am open to tech support engagement with anyone that has significant expertise in Artix 7, PCIe Gen 2 x4, especially wrt custom PCB. Simply reply to this post or message me with your contact information.

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470 Views
Registered: ‎02-16-2010

Re: Artix 7 PCIE Custom Board Issues with REFCLK

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Your observations mentioned in the initial thread seems to contradict.

 

In the paragraph below, you say that REFCLK is found inside the FPGA at least once in the custom board.

 

Reducing our full HDL system design to just the PCIE implementation with loopback we should be able to run the same bit file on both our AC701 prototype and our custom PCB. On the AC701 based system and during computer module boot we see proper operation. PERST negates, REFCLK is present, locks and the PCIE is recognized. However, on the PCB and during the computer module boot, we see the PERST negated and asserted 4 times. We see the REFCLK lock, then loose lock, then gain lock and then stop, but only during the first PERST negation. The REFCLK is never seen by the FPGA again after being lost during the first negation of PERST. This behavior was observed using Vivado and an ILA.

 

In the paragraph below, you mention that REFCLK is not seen at all in your custom board.

 

We also have another bit file that consists of no PCIE, but rather just the REFCLK connected to the IBUFDS_GTE2 and the PERST. When this bitfile is used on our AC701 based system we see the REFCLK and the four assertions of the PERST as the computer module attempts to recognize the PCIE. On the custom PCB based system the FPGA (using Vivado and an ILA) never sees the REFCLK at all, yet we can clearly see the REFCLK using the O-scope at the FPGA via.

 

As a further check, you can try the following. 

1. I find you are already forwarding the REFCLK to the FPGA fabric logic. Can you connect it an MMCM and probe the MMCM lock? Control the reset to the MMCM using a VIO.

 

2. If you can use PCIe integrated block IP, you can enable "JTAG debugger" feature to monitor the GT reset FSM status. Please try this also.

 

3. You can re-route the REFCLK to an output pin and probe it with an Oscilloscope. You can use the following clocking path to do this.

 

IBUFDS_GTE2 --> BUFG --> ODDR --> IO pin

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451 Views
Registered: ‎09-25-2013

Re: Artix 7 PCIE Custom Board Issues with REFCLK

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The issue has been resolved. The custom board was missing the AC decoupling capacitor on REFCLK.