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Teacher rcingham
Teacher
9,466 Views
Registered: ‎09-09-2010

Bad 'pcie_blk_plus_ll_rx.v' file (PCIe endpoint v1.13)

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FPGA: Virtex-5 FX100T

CoreGen: 11.4

IP: Endpoint Block Plus for PCI Express, v1.13

ISE: 14.2

 

The 'pcie_blk_plus_ll_rx.v' file that is generated does not compile.

The first error message is about an undefined macro, TCQ.

 


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"If it don't work in simulation, it won't work on the board."
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Teacher rcingham
Teacher
16,298 Views
Registered: ‎09-09-2010

Re: Bad 'pcie_blk_plus_ll_rx.v' file (PCIe endpoint v1.13)

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I note that the file generated by the v1.14 tool has the macro definition in it.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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2 Replies
Teacher rcingham
Teacher
9,465 Views
Registered: ‎09-09-2010

Re: Bad 'pcie_blk_plus_ll_rx.v' file (PCIe endpoint v1.13)

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The workaround is to copy the macro definition 

`ifndef TCQ
 `define TCQ 1
`endif

 from 'pcie_blk_plus_ll_tx.v', or one of the other files that defines it identically.

 

The error is with ISE PN working out its own compilation order, but I don't know enough Verilog to understand the subtleties of macro definition...

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Highlighted
Teacher rcingham
Teacher
16,299 Views
Registered: ‎09-09-2010

Re: Bad 'pcie_blk_plus_ll_rx.v' file (PCIe endpoint v1.13)

Jump to solution
I note that the file generated by the v1.14 tool has the macro definition in it.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos