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Observer sumaiya
Observer
195 Views
Registered: ‎10-29-2017

Can we use two PCIe with two block locations in XAZU5EV?

Hi,

      In zynq, XAZU5EV-SFV784-Q, Is it possible to have two PCIe RC in PL section? One PCIe with block location X0Y0, x2 @gen3 and another PCIe with block location X0Y1, x2 @gen3.

      When I tried to implement, Placement failed saying that it is incompatible with the device sometimes, sometimes implementation got successful. Can you please check on this and give me a clear idea on this? FYI, we have only one MGT bank in bank 224 where we have 4 MGTREFCLK pins and 8 transceiver pins. Is it really compatible? 

The error is : 

[Place 30-60] Place Check : This design requires more GTHE4_COMMON cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.

How to overcome this issue?

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2 Replies
Xilinx Employee
Xilinx Employee
170 Views
Registered: ‎05-08-2012

Re: Can we use two PCIe with two block locations in XAZU5EV?

Hi @sumaiya.

While there are two PCIE sites (X0Y0 & X0Y1), there is only one available GTHE4_COMMON (GTHE4_COMMON_X0Y1). There are actually 4 listed from a search, but only one is bonded/usable. I would check to see if there is a shared resources option in the IP core.


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unbonded.png
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Observer sumaiya
Observer
166 Views
Registered: ‎10-29-2017

Re: Can we use two PCIe with two block locations in XAZU5EV?

Hi marcb, 

     Yeah, please check.

Can you clarify whether two PCIes of same block location is possible (as both the blocks are in same bank)? Two PCIe of same block X0Y1 will work?  

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