11-13-2017 10:40 AM
I used the DMA bridge sub system to create PCI EP device.
The functional mode i use it as AXI bridge.
Now i created from this ip Example project,
which takes this ip and connect it to memory (Map AXI address to memory on FPGA)..
i did it with only 1 BAR and it worked fine...
Now lets say i'm doing same thing with 3 Bars,
How can i know from the AXI on which Bar i got hit? Where is this information is being coded?
11-14-2017 09:33 AM - edited 11-14-2017 09:34 AM
I see that you are using US+ device and using DMA//bridge IP iin bridge mode.
when you enbale multiple BARs (for multiple peripherals) all you have to do is simply build AXI interconnect accordingly.( say1 master three slave interconnect)
You need to provide correct PCIE to AXI address translation value for each BAR of corresponding AXI peripheral.
if the input MemWr request hits BAR1, the corresponding AXI address of peripheral_1 will be written into.
for details on how to mention address translation parameter, please go through the following AR.