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Observer bmoore
Observer
514 Views
Registered: ‎01-09-2018

DMA/Bridge subsys for PCIE in ZCU102?

Is there any equivalent for the DMA/Bridge subsys for PCIE IP that is offered for the Zynq US+ XCZU7EV, for the XCZU9EG that's on the ZCU102 dev board? There's a RTL PCIE block but it's not a complete solution. Is there any code out there that would give me the equivalent of that hard PCIE block that's in the 7EV? I wanted to test out a 7EV PCIE root design but I only have a ZCU102 dev board available.

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Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎08-02-2007

回复: DMA/Bridge subsys for PCIE in ZCU102?

Do you want to use PCIE DMA with PS PCIE

Have you checked out http://www.wiki.xilinx.com/XAPP1289+PCIe+Root+DMA

 

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Observer bmoore
Observer
470 Views
Registered: ‎01-09-2018

回复: DMA/Bridge subsys for PCIE in ZCU102?

Yes, I did. I need to implement the PCIe in the PL, not the PS, because I will be using the GTs in the PS fabric for other things. Also need the Gen 3 speed that the PL GTs offer. But thanks for responding.

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Moderator
Moderator
415 Views
Registered: ‎02-16-2010

回复: DMA/Bridge subsys for PCIE in ZCU102?

XCZU9EG device does not have a PCIe hard block. I hope you know this already. You will need to check for soft PCIe IP solutions.

If you check PCIexpress IP web page on Xilinx website, you can find references to IP partners - Nortwestlogic and PLDA.
https://www.xilinx.com/products/technology/pci-express.html
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