03-21-2019 01:41 AM
I'm using the DMA/Bridge subsystem for PCIe in bridge mode and wish to have two ethernet interfaces on the card side communicating to/from the host/root complex.
My understanding is that the DMA/Bridge IP (PG195) then is essentially identical to the PCI Express Integrated block (PG194). One difference I find is that the latter will have axi lite master and slave (M_AXI_LITE and S_AXI_LITE), while the former will only have an S_AXI_LITE conduit.
I have an intention of managing control from the host/root complex to the endpoint, not the other way around. Shouldn't a M_AXI_LITE be required for this?
Is there a workaround with an AXI interconnect, as in the figure above?
03-21-2019 02:23 AM
here you can found the complete project:
This project contains GPIOs for managing some control from the host/root complex to the endpoint.
Project was created within 2017.3 and succesfully tested for GPIOs and DDR3 on the KC705.
May be it will help.
03-21-2019 02:40 AM
03-21-2019 03:27 AM
New project -> ...-> KC705..-> IP Intergator -> Create Block Design -> Board -> PCIexpress -> Run Block Automation ->
-> ...->...PCI to AXI Lite Master Interface -> 1(Megabyte) ... or more.
Or better look here:
03-21-2019 03:57 AM