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Observer laurencebarker
Registered: ‎05-27-2018

DMA/bridge system on Artix 75: fails timing when compile

I am a relatively new FPGA designer. I'm using vivado 2018.3 and targeting an Artix device XC7A75TFGG484-1 or XC7A75TFGG484-2. My design has the Xilinx IP "DMA/bridge system for PCIe 4.1".

The project has a constraints file with timing constraints that were created using the timing wizard. There is only one constraints file in the design sources and it has my pin constraints (generated by me through editing the elaborated design) and wizard generated timing constraints. It includes definitions for the 125MHz and 250MHz clocks internal to the PCI express core. 

I have created a design in the Artix 75 with a software defined radio application (clocked at 122.88MHz) and a DMA/Bridge subsystem for PCI express. When I implement the project, I am getting several failures to meet timing constraints internal to the PCIe DMA core. These are in these groups:

intra-clock paths - clk_250mhz_Gen

inter-clock paths:

clk_125mhz to clk_250mhz_Gen

clk_125mhz_Gen to clk_125mhz


(when I ran the timing constraints wizard, it added these clock groups and they are listed in my constraints file:

create_generated_clock -name clk_125mhz_Gen -source [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I0] -divide_by 1 -add -master_clock clk_125mhz [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
create_generated_clock -name clk_250mhz_Gen -source [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1] -divide_by 1 -add -master_clock clk_250mhz [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks clk_125mhz_Gen] -group [get_clocks -include_generated_clocks clk_250mhz_Gen]




The DSP side of the project is OK: I have had some timing failures, but I understand the design and what I need to do to fix them. Mostly these are gone. 

My design uses 2/3 of the block RAM resources (62 block RAMs) in the FPGA: this might be an issue, because the DMA core uses quite a lot of memory. 


My questions are:

1. Should I have also included a DMA/bridge core specific constraints file; and if so where do I get it from. Or is it automatically included through instantiating the core. (PG195 page 86 says an XDC file with original, unmodified constraints needs to be used; it doesn't identify the file). (I can see from running report_compile_order -constraints that .XDC files for the PCIe core are already included)

2. Should I have allowed the timing wizard to create the 125MHz and 250MHz clock definitions, or are all those handled by constraints that belong to the PCIe core?



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