09-12-2018 07:00 PM
I use Xilinx K7 pcie IP core DMA/Bridge Subsystem for PCI Epress4.0 Vivado (2017.4), and select the AXI4-stream user interface. In the Windows 7 system applications, DMA reading and DMA writing can produce complete interrupt to driver after the completion of the data transmission, and data transceiver is normal. But, in Windows XP system applications, after the completion of the DMA reading and DMA writing, the driver can’t receive interrupt or in more than 20 minutes later. When I check the IP core status register, I can see engine_int_req (register 0x2044) is asserted ,engine_int_pending (register 0x204c) is asserted, and sometimes magic_stopped (register 0x40) is asserted. But if we don’t initiate dma operation, and only usr_irq_req is asserted, the transmission of interrupt to the driver is available. My question is why the driver cannot receive the completion interrupt after dma reading and writing in Windows XP system applications? Does the IP Core have interruptions in Windows XP application?
09-17-2018 04:16 PM
09-18-2018 06:23 PM
The XDMA driver I applied is not the driver provided by Xilinx official website, but generated by WinDriver. The phenomenon I provided can infer what happened to the IP kernel?Also, will the XDMA's IP core work on Windows XP system?