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Participant zguo
Participant
1,830 Views
Registered: ‎05-19-2017

General question about asynchronous clock constraints for PCIe

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The general rule of thumb with the clocks generated by the toolchain for the transceivers inside of the PCIe IP is that after a first run we should go and add constraints for those clocks to mark them as asynchronous to the main system clock to avoid timing failures. I have a design in Vivado 2017.1 where in the first run without those constraints passed timing. Has Vivado gotten better at this sort of thing, wherein the constraints that come as part of the generated PCIe IP are sufficient for this, or was this just a case of me getting really lucky?

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Historian
Historian
2,909 Views
Registered: ‎01-23-2009

Re: General question about asynchronous clock constraints for PCIe

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Virtex5 used ISE, which did not have the capability of automatically adding constraints to a project when an IP was added. Vivado does. Thus, if the clock crossing is done entirely in the IP, then it should be properly constrained by the IPs constraints.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: General question about asynchronous clock constraints for PCIe

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PCIE core has added many false path constraint within the core

please check the xdc file in the IP source tab for sure

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Historian
Historian
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Registered: ‎01-23-2009

Re: General question about asynchronous clock constraints for PCIe

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go and add constraints for those clocks to mark them as asynchronous to the main system clock to avoid timing failures.

 

In general, I would say that this is false, or at least extremely dangerous!

 

If a path exists between the PCI and main clock, then it must go through a proper clock domain crossing (CDC) circuit and be propery constrained. Simply declaring a path like this false (or the clocks asynchronous) is wrong.

 

That being said, if the clock crossing is done inside the PCIe core itself, then the IP core will have proper clock domain crossing, and the scoped XDC file that goes along with the IP core will have proper timing exceptions for these CDCs.

 

Furthermore, if this is the case, and you then go and declare the clocks as asynchronous, you will be overriding the proper constraints from the scoped XDC, and thus breaking the clock domain crossing circuit within the IP.

 

If you have clock domain crossing paths outside the IP core, then you need to ensure that you have a CDC circuit for the crossing, and proper constraints for that CDC. In general (actually, pretty much always in a system like this) an asynchronous clock group is not the correct thing to do.

 

For more on this, take a look at this post (and the posts referenced within that pos) on constraining CDCs.

 

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Participant zguo
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Registered: ‎05-19-2017

Re: General question about asynchronous clock constraints for PCIe

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That much I can see. My question is has Xilinx's guidance about the usage of set_clock_groups like in AR #44651 changed for the newer versions of Vivado and the associated IP?

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Participant zguo
Participant
1,791 Views
Registered: ‎05-19-2017

Re: General question about asynchronous clock constraints for PCIe

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New message popped in and I didn't realize when I posted prior response. The reason I make mention of adding in the constraints directly is because most of the example designs do just that, like with XTP444 for the VCU118 or XTP207 for the VC707. And I remember specifically having to do some constraining for the even older Virtex5 back in the ISE days.

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Historian
Historian
2,910 Views
Registered: ‎01-23-2009

Re: General question about asynchronous clock constraints for PCIe

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Virtex5 used ISE, which did not have the capability of automatically adding constraints to a project when an IP was added. Vivado does. Thus, if the clock crossing is done entirely in the IP, then it should be properly constrained by the IPs constraints.

 

Avrum

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Participant zguo
Participant
1,717 Views
Registered: ‎05-19-2017

Re: General question about asynchronous clock constraints for PCIe

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Good to know, makes life much easier.
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