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Hardcode power limit value for PCIe core

Posts: 16
Registered: ‎05-10-2017

Hardcode power limit value for PCIe core

In the docs I can see that we can set the power limit value/scale in "device capabilities register" through the configuration interface. I was wondering if it's possible to hard code the value at synthesis time as a parameter to the module.

Posts: 2,770
Kudos: 353
Solutions: 252
Registered: ‎02-16-2010

Re: Hardcode power limit value for PCIe core

With UltraScale+ PCIe IP, I can find that there are two signals that can help with your requirement --cfg_msg_transmit_type, cfg_msg_transmit_data.

Please check the description of these signals in PG213.
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