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Explorer
Explorer
614 Views
Registered: ‎03-06-2014

How to constraint the Differential clock and reset pins in PXIe-700 incliuding a KINTEX-7?

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Dear all,

 

I am using the PXIe-700 Card provided by Sundance including a KINTEX-7 (xc7k410t FFG900) board (more info here). I do not know where are the differential reference clocks location to connect to AXI Menory Mapped to PC Express module in block design? Also, the reset pin location was not mentioned in its User Guide. I always get the following error message in bitstream generation process:

 

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: refclkp[0], and refclkn[0].

Can anyone help me to solve this issue? Thanks in advance for your care and consideration.

 

Bests,

 

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1 Solution

Accepted Solutions
Adventurer
Adventurer
427 Views
Registered: ‎08-30-2018

Re: How to constraint the Differential clock and reset pins in PXIe-700 incliuding a KINTEX-7?

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Just use the constranitsto located the PCIe channelas follows. You can also do the same for the differential clock.

 

set_property PACKAGE_PIN M5 [get_ports {pcie_rxn[0]}]
set_property PACKAGE_PIN M6 [get_ports {pcie_rxp[0]}]

repeat it for how many channels that you have.

 

Hope it works!

 

3 Replies
Explorer
Explorer
590 Views
Registered: ‎03-06-2014

Re: How to constraint the Differential clock and reset pins in PXIe-700 incliuding a KINTEX-7?

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Also, here is the snapshot of my refclk and resetn pins. I do not know how to constraint them in my XDC file ?!!

 

 

refclk_resetn.png
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Moderator
Moderator
572 Views
Registered: ‎02-16-2010

Re: How to constraint the Differential clock and reset pins in PXIe-700 incliuding a KINTEX-7?

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Based on 4.1.1 section in Appendix, it seems PCIe is mapped to quad 115 and refclk is mapped to U8/U7 differential pair.

In that table, PRSNT# seems to be the PCIe reset input. But there is no LOC specified in the document. Please check with the vendor to get this details.
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0 Kudos
Adventurer
Adventurer
428 Views
Registered: ‎08-30-2018

Re: How to constraint the Differential clock and reset pins in PXIe-700 incliuding a KINTEX-7?

Jump to solution

Just use the constranitsto located the PCIe channelas follows. You can also do the same for the differential clock.

 

set_property PACKAGE_PIN M5 [get_ports {pcie_rxn[0]}]
set_property PACKAGE_PIN M6 [get_ports {pcie_rxp[0]}]

repeat it for how many channels that you have.

 

Hope it works!