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Visitor eibach
Visitor
574 Views
Registered: ‎07-02-2018

KC705 PCIe clock in block design

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I place the XDMA subsystem and run automation functions in the block design. The PCIe clock gets connected to a 20 MHz sysclock instead of the clock signal from the PCIe connector. What is the right way to fix this?

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1 Solution

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Moderator
Moderator
463 Views
Registered: ‎02-16-2010

Re: KC705 PCIe clock in block design

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You can follow the steps below.
1. synthesize the design
2. Open the synthesized netlist
3. Change the layout (Top right) in vivado as "IO Planning" layout
4. Check the IO ports window to know the LOC of sys_diff_clk.
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5 Replies
Moderator
Moderator
540 Views
Registered: ‎02-16-2010

Re: KC705 PCIe clock in block design

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Which VIVADO version are you using?

While creating the project, have you selected KC705 board?
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Visitor eibach
Visitor
525 Views
Registered: ‎07-02-2018

Re: KC705 PCIe clock in block design

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I am using Vivado 2018.2 and selected the KC705 board when creating the project. All other lines are connected correctly.

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Moderator
Moderator
505 Views
Registered: ‎02-16-2010

Re: KC705 PCIe clock in block design

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This looks to be an issue with the block automation. You can edit the properties of sys_diff_clock to 100MHz to fix the issue. The snapshot below shows this option.

sys_diff_clk.JPG

 

The command below also can help to update the frequency.

set_property CONFIG.FREQ_HZ 100000000 [get_bd_intf_ports /sys_diff_clock]

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Visitor eibach
Visitor
474 Views
Registered: ‎07-02-2018

Re: KC705 PCIe clock in block design

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Ok, setting the frequency resolves the error message.

But is the signal sys_diff_clock really connected to the PCIe-connector clock? HJow can I check this?

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Moderator
Moderator
464 Views
Registered: ‎02-16-2010

Re: KC705 PCIe clock in block design

Jump to solution
You can follow the steps below.
1. synthesize the design
2. Open the synthesized netlist
3. Change the layout (Top right) in vivado as "IO Planning" layout
4. Check the IO ports window to know the LOC of sys_diff_clk.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos