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4,666 Views
Registered: ‎12-05-2016

Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

My setup: Using a ZCU102 Zynqmp Ultrascale+ MPSoC (ZU9) as the root complex in my PCIe setup, I have mezzanine card connected to the PCIe slot acting as a PCIe End Point. I would like to connect to it from a program running on the R5 (or A53) running the Standalone (Bare Metal) kernel. I am using the Programmable Subsystem (PS) PCIe interface, not the AXI connected Programmable Logic (PL) PCIe connection. We are using a x1 lane and Gen 1 PCIe. I am using the Xilinx 2016.3 release.

 

My questions:

Is there a Standalone PS driver for the PCIe? I see the PL one (Xilinx AXI PCIe IP (XAxiPcie)), but I do not see an equivalent one for the "ps".

 

Also, I am looking for some sample code that sets up the PCIe device and writes and reads from PCIe mapped registers or memory.

 

Lastly, is there any thing like a showPCI command that prints information about all discovered devices on the PCIe bus?

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Xilinx Employee
Xilinx Employee
4,513 Views
Registered: ‎11-25-2015

Re: Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

hi @braetontaylor,

 

I am not sure about the driver details

 

But a path does exist to DMA from PS PCIe to PL, we recommend that customers move data to the PS DDR first.  Going through the CCI and Core Switch can have latency causing system timeout.  It really depends on how much data is in those paths and if a timeout will happen.

 

I’ve included a diagram with the paths highlighted.

 

Thanks,

Sethu

Zynq MPSOC.jpg
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4,455 Views
Registered: ‎12-05-2016

Re: Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

Thanks, but that does not help with my problem.  I am trying to use the PS-side PCIe from a bare metal application running on the R5 to talk to a device in the PCIe slot that is acting as an end point.  I am looking to see if anyone has setup a PCIe device from a bare metal application and then used that setup to access registers/memory on the end point device.

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Visitor hf2
Visitor
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Registered: ‎03-28-2017

Re: Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

I am in the same boat as baeton in looking for a PS solution to controlling the PCIe in a standalone application (since Linux is causing timing issues for my design). It seems the available PCIe drivers (XAxiPcie) were designed for the Kintex and Virtex boards. I've been looking into a PS to PL workaround from a different thread that seems to follow sethus' advice and adapting it to the zcu102.

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Scholar hbucher
Scholar
3,431 Views
Registered: ‎03-22-2016

Re: Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

@braetontaylor  You could basically rip off the Linux driver and make it a standalone driver. Kernel protected programming is not that much different of standalone programming. That is what I did with the SI570  programmable oscillator for the tengig component. 

But no, I have not done that before - just throwing some options here.

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Visitor nik_dan
Visitor
2,187 Views
Registered: ‎01-17-2018

Re: Looking for Zynqmp Ultrascale+ MPSoC PCIe PS side example code (Standalone, not Linux)

Hello,

 

I am looking for the same solution.

 

Have you completed the bare Metal PS side driver for PCIe. I want to transfer data from fabric to PCIe through DMA.

 

 

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