09-17-2018 05:29 AM
we have a device based on Artix-7 (xc7a35t-2csg325t) which uses 7 Series FPGAs Integrated Block for PCI Express v3.3 (2.0 x 1) and own custom TLP/DMA engine with bus mastering.
One of our customer faced a weird issue on new Intel H370 chipset (Gigabyte H370 HD3 motherboard) - all DMA transfers hangs from every start. But all host -> card (not bus mastering) requests are working.
After some investigation we'd noticed that:
Further, we have implemented minimal design with DMA/Bridge subsystem for PCI Express (XDMA):
and got same issue - no completion from host, xdma engine hangs (xdma_test.exe freezes at h2c testing). So, this problem isn't related to our TLP/DMA...
Moreover, xdma works perfectly on Linux in same configuration!
Looks like something prevents our card from reading host memory, but for example, in case of IOMMU faults host usually responses with error completion, here we can see nothing...
Likely, it's problem with chipset configuration or even with software (windows?). Maybe it's Gigabyte's fault.
Does anyone faced such weird behavior?
Does anyone tried Integrated Block for PCI Express and bus mastering on H370 platforms?
What it could be?
What else can we try?
09-26-2018 01:44 AM
The first test I would recommend is to use the out of the box example design to see if this works first? You can use Gen1 x1 as a simple test. If the same behaviour is seen this will provide you a baseline starting point to debug. Can you try this?
09-27-2018 07:49 PM
That design with XDMA we had tried was already Gen 1 x1.
Example design provided with Integrated Block IP (PIO) works perfectly - because it only replies to host with completions, without any bus mastering. And as I said, device is receiving requests from host and sending completion to host without any issues. But if device is sending requests to host (bus mastering) it has no any completion from it at all.