UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor jaredfrank
Visitor
6,617 Views
Registered: ‎09-21-2009

PCI Configuration Space and DMA question

I have two questions. I am new to using the EDK and PCI Express (more familiar with PCI and strict vhdl). I just purchased an ML507 and I am trying to prototype a board. My first question is a simple one. The PLBv46 Bridge Manual says that the Vendor ID and Device ID can be changed (Page 8 of the PLBv46 Bridge for PCI Express). Here is the code I am currently using:

 

while ( XPcie_mReadReg( XPAR_PCIE_BRIDGE_BASEADDR, XPCIE_EBUS_SR_OFFSET ) & XPCIE_EBUS_SR_LU_MASK != XPCIE_EBUS_SR_LU_MASK );
XPcie_mWriteReg( XPAR_PCIE_BRIDGE_BASEADDR, XPCIE_BCR_OFFSET, 0x003f0107 );
XPcie_mWriteReg( XPAR_PCIE_0_BASEADDR, XPCIE_IPIF2PCI_0U_OFFSET, 0x00000000 );
XPcie_mWriteReg( XPAR_PCIE_0_BASEADDR, XPCIE_IPIF2PCI_0L_OFFSET, 0x00000000 );

ConfigPtr = XPcie_LookupConfig( 0 ); 
XPcie_CfgInitialize( PciePtr, ConfigPtr, ConfigPtr->BaseAddress );

XPcie_PciHeaderWrite( PciePtr, XPCIE_HDR_VENDOR, 0xFFFFFFFF ); 

This code however doesn't work. The default Xilinx Device and Vendor IDs are kept (that is, my write is ignored). What do I need to do to fix this problem. Note that this is almost right out of the examples, and the code executes just fine (minus the fact that the write is ignored).

 

When I wrote this sort of thing using PCI it was much easier but I had complete control of everything. My second question is more about DMA. My previous PCI prototype could read PC Host memory (RAM residing on the PC and not in the FPGA) by sending a Bus Master request. This was realtively simple to write with VHDL. I would do this by simply plaing the address that I wanted to write on the PCI bus, and the MCH would come back with a response. My problem is I am having a problem understanding how to do this with the EDK. Keep in mind that I am new to developing with the PPC and the PLB in general.

 

Could someone give me an example of how you would read say address range 0x70000000-0x700000FF on the Host PC from within the EDK.

 

I appologize for the long question but I have been trying to figure this out for almost 2 weeks, and I have read everthing I can find with no success. I thank you in advance for assisting.

 

0 Kudos
2 Replies
Visitor jaredfrank
Visitor
6,612 Views
Registered: ‎09-21-2009

Re: PCI Configuration Space and DMA question

Well I think I may have answered one of my own questions. I did a system wide search for the symbol C_VENDOR_ID and found an MHS file. In this file you can set the parameters for the different devices used by the EDK. The parameters for the PLBv46 Bridge for PCI Express are in this file. Just goes to show how terrible the documentation is. Maybe I just missed it, but I was unable to find this anywhere in the documentation for the PLBv46.

 

So with that said, I am still having trouble understanding the address translation for PCI Express and the PLB (that is, my second question is still unanswered).

 

Thanks

0 Kudos
6,444 Views
Registered: ‎09-30-2009

Re: PCI Configuration Space and DMA question

I would recommend reading the plbv46 endpoint bridge for pcie express document. DS540

These is a section on address translation that you will find helpful. 

 

What you need to do is set up the IPIF BARs for your desired address mappings.

 

If you are in the edk open up the system assembly view.  Make sure you are in either the bus interface or ports tab. You can now right click on the pcie_bus and select configure. Under user>>IPIF bar you will find the settings for address translation.

0 Kudos