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Observer fsgaglione
Observer
549 Views
Registered: ‎12-27-2018

PCI Express Bridge simulation

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Hello,

I'm trying to set up a simulation environment (IRUN Cadence tools) for a project containing a PCIe bridge (DMA / Bridge Subsystem for PCI Express (PCIe) version 4.1). For the simulation I'm trying to compile the source files of the bridge generated by the synthesis of the Block Design. At the moment Cadence tool gives me an error on the hidden instances (xdma_v4_1_1_udma_wrapper ...) because they are not in the libraries generated using "Compile Simulation Libraries". How can I compile these hidden files in my environment?

 Capture.PNG

Error generated by IRUN Cadence tools:

udma_wrapper (
|
ncelab: *E,CUVMUR (./Wrapper/xbridge/PCIe_Bridge_system_xdma_0_0_core_top.sv,4294|14): instance 'tb_top.PCIe_Bridge_system_i@PCIe_Bridge_system<module>.xbridge_0@PCIe_Bridge_system_xdma_0_0<module>.inst@PCIe_Bridge_system_xdma_0_0_core_top<module>.udma_wrapper' of design unit 'xdma_v4_1_1_udma_wrapper' is unresolved in 'worklib.PCIe_Bridge_system_xdma_0_0_core_top:sv'.

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
Tags (1)
1 Solution

Accepted Solutions
Moderator
Moderator
439 Views
Registered: ‎02-11-2014

Re: PCI Express Bridge simulation

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Hello @fsgaglione,

I took your XCI file and build the IP Example Design using it. I pre-compiled my simulation libraries in IUS 15.20.042 for Vivado 2018.2.2. I ran export_simulation on the IP Example Design and then ran through the provided sample script and ran into no issues.

I have uploaded my simulation scripts for your analysis. Please let me know if they help in your debug.

Thanks,
Cory

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7 Replies
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Moderator
Moderator
516 Views
Registered: ‎02-11-2014

Re: PCI Express Bridge simulation

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Hello @fsgaglione,

Could you let me know which version of Cadence IUS you are using to simulate with? Could you also explain your simulation flow for me?

Thanks,
Cory

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Observer fsgaglione
Observer
482 Views
Registered: ‎12-27-2018

Re: PCI Express Bridge simulation

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I'm using the incisive 15.20.026.

for compilation I use many lines as:

ncvlog -MESSAGES -NOLOG -CDSLIB cds.lib -HDLVAR hdl.var -64bit +incdir+./Libs/.cxl.ip/incl -sv -work xdma_v4_1_1 -f ./CMF_file

for simulation:

irun   -sv -messages -64BIT \
         -cdslib ./cds.lib \
         -V93 \
         -incdir ./Libs/.cxl.ip/incl \
         -incdir /apps/xilinx/2018.2/Vivado/2018.2/data/xilinx_vip/include \
         -file ./NVMe_Capture_files.cmf
         -access rw \
         -ncelabargs "tb_top" \
         -timescale "1ns / 1ps" \
         -gui

The design block includes a processor that communicates with the outside via the PCIe bridge. In addition I made an IP (NVMe_Capture_files) capable of reading the information that the processor exchanges with the bridge. I need to simulate the project except the processor that I will replace with one of my test blocks. The realized IP is correctly compiled while the bridge, during simulation, generates the error mentioned above.

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
Moderator
Moderator
460 Views
Registered: ‎02-11-2014

Re: PCI Express Bridge simulation

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Hello @fsgaglione,

Could you also please zip up your XCI file and provide it for debug as well? I would like to verify your core configuration as the simulation filelist differs from config to config.

Thanks,
Cory

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Observer fsgaglione
Observer
449 Views
Registered: ‎12-27-2018

Re: PCI Express Bridge simulation

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Hi coryb,

this is the XCI file of the Bridge PCIe.

 

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
0 Kudos
Moderator
Moderator
440 Views
Registered: ‎02-11-2014

Re: PCI Express Bridge simulation

Jump to solution

Hello @fsgaglione,

I took your XCI file and build the IP Example Design using it. I pre-compiled my simulation libraries in IUS 15.20.042 for Vivado 2018.2.2. I ran export_simulation on the IP Example Design and then ran through the provided sample script and ran into no issues.

I have uploaded my simulation scripts for your analysis. Please let me know if they help in your debug.

Thanks,
Cory

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer fsgaglione
Observer
395 Views
Registered: ‎12-27-2018

Re: PCI Express Bridge simulation

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Hi coryb

thanks for your support, now I can compile and simulate my project.

This is how I use IRUN:

  irun   -sv -messages -64BIT \
         -cdslib ./cds.lib \
         -NOCOPYRIGHT -LICQUEUE \
         -nowarn COVFHT \
         -nowarn CUFEPC -nowarn WARIPR \
         -nowarn INTOVF -nowarn CUVWSP \
         -nowarn CUVMWP -nowarn BNDMEM \
         -nowarn IGNFMT -nowarn CUVIHR \
         -nowarn CUVWSP -nowarn CUVMPW \
         -nowarn BIGWBS -nowarn REALCV \
         -nowarn CSINFI -nowarn WARIPR \
         -nowarn CUVWSP \
         -nowarn CUVMPW -nowarn BNDMEM \
         -nowarn CFMPWM -nowarn COVDNC \
         -nowarn TSNSPK -nowarn FUNTSK \
         -nowarn UEXPSC -nowarn DUPBWA \
         -nowarn SAWSTP -nowarn DUPBWA \
         -nowarn SYSFMW -nowarn TMSERX \
         -nowarn BIGWIX -nowarn ZROMCW \
         -nowarn SYSFMW -nowarn RTSDAD \
         -nowarn SPDUSD -nowarn OBINXZS \
         -errormax 3 \
         -V93 \
         -relax \
         -incdir ./Topfiles/NVMe_Capture \
         -incdir ./Topfiles/Wrapper \
         -incdir ./Topfiles/Wrapper/xbridge/include \
         -incdir ./Xilinx_libs/.cxl.ip/incl \
         -incdir /apps/xilinx/2018.2/Vivado/2018.2/data/xilinx_vip/include \
         -f ./Topfiles/NVMe_Capture/topfiles.cmf \
         -f ./Topfiles/Wrapper/run.cmf \
         -f ./Topfiles/Wrapper/TopWrapper.cmf \
         -top glbl \
         -access rw \
         -ncelabargs "tb_top" \
         -timescale "1ns / 1ps" \
         -log PippoPluto.log \
         -gui \
         -INPUT runsim.tcl \
         -status

but by running the script I get some Warnings:

  ncvlog: *W,MACRDF (./Topfiles/Wrapper/xbridge/include/pciedmacoredefines.vh,143|36): text macro 'XPREG' redefined - replaced with new definition.
(`include file: ./Topfiles/Wrapper/xbridge/include/pciedmacoredefines.vh line 143, `include file: ./Topfiles/Wrapper/xbridge/include/xdma_axi4mm_axi_bridge.vh line 3, file: ./Topfiles/Wrapper/xbridge/PCIe_Bridge_system_xdma_0_0_dma_bram_wrap.sv line 59)

 

  `include "dma_defines.svh"
|
ncvlog: *W,NORECI (./Topfiles/Wrapper/xbridge/include/dma_pcie_dsc_in_if.svh,3|25): input source text recursion detected for './Topfiles/Wrapper/xbridge/include/dma_defines.svh' (`include source file).
(`include file: ./Topfiles/Wrapper/xbridge/include/dma_pcie_dsc_in_if.svh line 3, `include file: ./Topfiles/Wrapper/xbridge/include/dma_defines.svh line 365, file: ./Topfiles/Wrapper/xbridge/PCIe_Bridge_system_xdma_0_0_dma_bram_wrap.sv line 61)
interface worklib.dma_pcie_dsc_in_if:svh

 

  ncelab: *W,CUSRCH: Resolved design unit 'xdma_v4_1_1_udma_wrapper' at 'udma_wrapper' to 'xdma_v4_1_1.xdma_v4_1_1_udma_wrapper:module' through a global search of all libraries.

 


  ncelab: *W,CUSRCH: Resolved design unit '{*Name Protected*}' at '{*Name Protected*}' to 'xdma_v4_1_1.{*Name Protected*}:{*Name Protected*}' through a global search of all libraries.

 

  ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.


  ncelab: *W,STARMT: This @* expands to empty list, will never wake up.

 

  ncelab: *W,BNDASW (/apps/xilinx/2018.2/Vivado/2018.2/data/ip/xilinx/xdma_v4_1/hdl/xdma_v4_1_vl_rfs.sv): warning within protected source code.

 

  ncsim: *W,NOCOND: Unique case violation: Every case item expression was false.
  Scope: {*Name Protected*} Time: 0 FS + 27

 

These Warnings can create problems in simulation or in the comportament of the IPs?

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
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Moderator
Moderator
361 Views
Registered: ‎02-11-2014

Re: PCI Express Bridge simulation

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Hello @fsgaglione,

None of these warnings look concerning to me.

Thanks,
Cory

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