I am having trouble getting the inputs of the 7 Series Integrated Block for PCI Express example to have any influence on the outputs. This is an example that is part of the Vivado IP Catalog under Standard Bus Interfaces. When I don't change anything the default for the inputs cor_pci_exp_rxp and cor_pci_exp_rxn are 'U' and the outputs cor_pci_exp_txp and cor_pci_exp_txn change independently. I can not determine what is causing them to change since the inputs are just 'U'. If I try and force the inputs to be just B"1" in the simulation source files the inputs are still 'U' in the simulation file. Can someone please explain to me what I should be doing to send data through the PCI Express?
Product family: Artix-7
Project part: xc7a200ftbg484-1
Target language: VHDL
which version of the vivado tool you are using?
I have tried simulation in 2018.2 version of the tool, I was able to see the data transfers, check the attached snapshot
could you attach your .xci ip file
example design created for the .xci you have attached works fine.
Can you click on restart in the simulator and again click on run all and wait until the simulation is completed?