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Observer elefferd
Observer
555 Views

PCI Express Example

I am having trouble getting the inputs of the 7 Series Integrated Block for PCI Express example to have any influence on the outputs. This is an example that is part of the Vivado IP Catalog under Standard Bus Interfaces. When I don't change anything the default for the inputs cor_pci_exp_rxp and cor_pci_exp_rxn are 'U' and the outputs cor_pci_exp_txp and cor_pci_exp_txn change independently. I can not determine what is causing them to change since the inputs are just 'U'. If I try and force the inputs to be just B"1" in the simulation source files the inputs are still 'U' in the simulation file.  Can someone please explain to me what I should be doing to send data through the PCI Express?

 

Simulation.PNG

 

Product family: Artix-7

Project part:  xc7a200ftbg484-1

Target language: VHDL

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5 Replies
Moderator
Moderator
450 Views

Re: PCI Express Example

which version of the vivado tool you are using?

I have tried simulation in 2018.2 version of the tool, I was able to see the data transfers, check the attached snapshot

could you attach your .xci ip file

pcie_artix.JPG
Observer elefferd
Observer
419 Views

Re: PCI Express Example

I am using 2018.2 as well. Here is my .xci ip file.

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Moderator
Moderator
408 Views

Re: PCI Express Example

Hi @elefferd,

 

example design created for the .xci you have attached works fine.

Can you click on restart in the simulator and again click on run all and wait until the simulation is completed?

 

 

--Krishna

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Observer elefferd
Observer
393 Views

Re: PCI Express Example

If I try run all it just runs continuously and does not stop. I get past the point of your simulation and it is still "U". Simulation.PNG

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Observer elefferd
Observer
341 Views

Re: PCI Express Example

@kkn is it possible that the free version of Vivado would cause a problem simulating this?

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