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Explorer
Explorer
325 Views
Registered: ‎05-14-2017

PCIe 7-series integrated block 3.3

I have implemented the PCIe into my design and it is working well for a payload of up to 3DW.

All the axis_rx and axis_tx function, timing  and interface are good from the hw_ila.

 

What acts strange is when I send a payload of more than 3 DW from the software side. I'm using the "memcpy" function to perform the read and write function.My Max payload size is 512 byte that is set from the IP Wizard.

 

The axis_rx side is not receiving ONE PCIe packet with 4 DW payload but instead it is broken up into multiple PCIe packets.

For example, if I send four DW labeled as DW1, DW2, DW3, DW4

 

Packet#1 starts from PCIe  addr0 and only DW1, DW2

Packet#2 starts from PCIe addr4 and contain DW2

Packet#3 starts from PCIe addr0 and contain the same DW1, DW2 (same as packet#1)

Packet#4 starts fromPCIe  addr4 and contain DW2 (repeat again)

Packet#5 starts from PCIe addrC and contains DW4

Packet#6 starts from PCIe addr8 and contain  DW3

 

When you add them all up you do get DW1, DW2, DW3, DW4 but why is it all broken up and received out of order?

It is very hard to process these six packet because they are out of order and are fragmented. Since they do not always ends with the last DW, one cannot tell when it is the last packet received. This example it ends with DW3.

 

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1 Reply
Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎07-26-2012

Re: PCIe 7-series integrated block 3.3

Completions with the same Transaction ID must not pass each other per PCIe base specification. Does read / write operations do to the direct link partner of the FPGA? Or is it via switch or bridge?

 

Do you know if the link partner reports Replay Timer Timeout error as it seems to be retransmitting the same data?