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Newbie dooheon0527
Newbie
193 Views
Registered: ‎09-17-2018

PCIe BAR based DRAM memory access is very slow

 Hi guys,

I implemented Memory module which was connected to Desktop through PCIe

Configuration is

Host - PCIe - | xilinx PCIe core - axi interconnect - MIG - DRAM |

I set two BAR region in PCIe core. And the second BAR region is mapped to axi address range.

This is the FPGA hardware setting.

 

And software, I set the cdev driver which access address of PCIe bar2 MMIO by ioremap()

 

But, FPGA memory's latency is too slow. 

read is about 2us...  write is about 1.3us..

 

Is this typical performance?

Or I have some mistake?

If anyone who implement this system or the similar one, tell me what is the performance of your system.

 

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1 Reply
Moderator
Moderator
89 Views
Registered: ‎02-11-2014

Re: PCIe BAR based DRAM memory access is very slow

Hello @dooheon0527,

Could you please provide your Block Diagram or a Testcase to reproduce your issue? Which architecture is this in? Which Driver are you using? Which PCie IP are you using?

Thanks,
Cory

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