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Visitor stast
Visitor
9,542 Views
Registered: ‎02-27-2009

PCIe BAR size

Hi,

 

Is it possible to change the BAR size after having already configured the core from coregen?

In other words, is there any way to change the amount of the requested memory space without having first to re-run coregen?

 

Thanks in advance,

stast

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5 Replies
Adventurer
Adventurer
9,514 Views
Registered: ‎02-26-2009

Re: PCIe BAR size

Hi,

 

As far as I know, there are some informations maybe useful to you.

1.In PCIE Specification, the root read memory space request in your design stored in a register at the initializing process, and then give the PCIE endpoint a memory space less or equal to the request. I mean it is quite possible for the Endpoint to get more memory space than it required only if the root are designed to do so in your system.

2.The function of memory space is that when a TLP using memory-routing method such as a memory write TLP, the bridge transmit the TLP to the correct endpoint according to the memory space. So a large memory space is not necessary, unless you are designing a RAM or such thing like that. You can defer different TLP by the content rather than by memory address.

 

--fox

note :I am a non-native English speaker, but I've tried to inllustrate my view as clear as possible. If there are any mistakes plz point out, thank you very much.

Regards,
Hu LI
Xilinx Employee
Xilinx Employee
9,493 Views
Registered: ‎08-01-2007

Re: PCIe BAR size

Hi Stast,

 

Unfortunately, no, there is no way to change the size of space requested by a BAR in the Endpoint core without re-generating via coregen.  The read/write-able bits in each BAR in the core are set when the core is generated.

 

-Kyle

Visitor steuerm
Visitor
6,037 Views
Registered: ‎01-30-2014

Re: PCIe BAR size

The BAR mask is auto-generated by Coregen... But can you simply change the value in the source directly? For example, I have a PCIe Endpoint core entitled s6_pcie_v2_4.  Can't I change the value of BAR0 directly in that source without regenerating the core?  I think I can, because my host is recognizing the new allocated space after changing just that parameter.  Are there any other dependencies other than the BAR parameters in the core source?

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Scholar markcurry
Scholar
6,032 Views
Registered: ‎09-16-2009

Re: PCIe BAR size

FYI -

 

I've exposed the the BAR1/BAR0 paremeters from the generated core, and reconfigured them at my top level design, with no issues.

 

We do this often with Xilinx "wizard" generated IP.  Sometimes if we're unsure we'll do A/B comparison with two autogenerated cores to confirm that the auto-generated core is just changing the parameter. 

 

More often we just give the code a quick inspection, expose the paramater, and move on without the A/B comparison check.

 

Regards,

 

Mark

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Visitor steuerm
Visitor
6,022 Views
Registered: ‎01-30-2014

Re: PCIe BAR size

So you're saying that the core does not have to be regenerated if we want to change the BAR size... Just has to be changedin the top level core wrapper. Is that correct?
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