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Explorer
Explorer
9,673 Views
Registered: ‎12-01-2010

PCIe Core ver 3.0 - Shared Clocking trouble

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Hello,

I have a working PCIe design that implements internal clocking.  It runs fine and is reliable, but i still have trouble closing timing INSIDE the core.  I attempted to enable "Include Shared Logic (Clocking) in example design" to allow me to drive the clocking from the outside to control timing better, as suggested in PG054.

On power up of the PC, the clock is running, and the Link trains.  However, the PC doesn't boot.  I must be doing something wrong with driving the clocks.  Are there any guidelines on what all the clocks are supposed to be?
IE, are the userclocks always the same or always different?

I have verified that i am generating clocks as indicated in PG054, page 191

• clk_125mhz - 125 MHz clock.
• clk_250mhz - 250 MHz clock.
• userclk - 62.5 MHz / 125 MHz / 250 MHz clock, depending on selected PCIe core lane width, link speed, and AXI interface width.
• userclk2 – 250 MHz / 500 MHz clock, depending on selected PCIe core link speed.
• oobclk – 50 MHz clock.


I've tried a dozen different configurations, and none seem to make the PC boot, despite the Link being Trained.

What am i doing wrong?  How do i find out where the system is being held up?



Current system: Vivado 2013.4, 7 Series Integrated Block for PCIe v3.0, Gen 2 x8, VC707 dev board.

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Explorer
Explorer
16,352 Views
Registered: ‎12-01-2010

Re: PCIe Core ver 3.0 - Shared Clocking trouble

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Koti,
Thank you for your response.
I went back and generated the PIO example for the core.  Using that, i was able to determine the appropriate timing settings that are required on the input generics.  This gave me the solution.  I had the PCIE_USERCLK1_FREQ set incorrectly at 4 instead of 5.

For an 8x Gen 2, the input parameters for the Pipe_clock.v file should be as follows:

 parameter PCIE_ASYNC_EN      = "FALSE",     // PCIe async enable
 parameter PCIE_TXBUF_EN      = "FALSE",     // PCIe TX buffer enable for Gen1/Gen2 only
 parameter PCIE_CLK_SHARING_EN= "FALSE",     // Enable Clock Sharing
 parameter PCIE_LANE          = 8,           // PCIe number of lanes
 parameter PCIE_LINK_SPEED    = 3,           // PCIe link speed
 parameter PCIE_REFCLK_FREQ   = 0,           // PCIe reference clock frequency
 parameter PCIE_USERCLK1_FREQ = 5,           // PCIe user clock 1 frequency
 parameter PCIE_USERCLK2_FREQ = 4,           // PCIe user clock 2 frequency
 parameter PCIE_OOBCLK_MODE   = 1,           // PCIe oob clock mode
 parameter PCIE_DEBUG_MODE    = 0            // PCIe Debug mode

 

Using these settings allowed to system to boot up without issues.

This leads me to point out that the data sheet PG054 is incorrect.  On page 191, it says the following:

userclk - 62.5 MHz / 125 MHz / 250 MHz clock, depending on selected PCIe core lane width, link speed, and AXI interface width.

 

A value of 5 gives the USERCLK1 a frequency of 500 MHz.  This is not listed as a possible value!  Please fix this so that others may not have the same problem.

 

In addition, it lists only one posibility for the OOBCLK:

 

oobclk – 50 MHz clock

 

The PIO design uses a value of 1, which is equal to 62.50 MHz.  This also should be listed as a possibility in this section.


Thank you for your help.

Mark

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Scholar kotir
Scholar
9,642 Views
Registered: ‎02-03-2010

Re: PCIe Core ver 3.0 - Shared Clocking trouble

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Hi Markzak,

does the timing failure occurs with the default example design ?
Can you post the xci file and timing report ?

When PC does not boot , is there any Bios errors seen ?

Regards,
Koti Reddy

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Explorer
Explorer
16,353 Views
Registered: ‎12-01-2010

Re: PCIe Core ver 3.0 - Shared Clocking trouble

Jump to solution

Koti,
Thank you for your response.
I went back and generated the PIO example for the core.  Using that, i was able to determine the appropriate timing settings that are required on the input generics.  This gave me the solution.  I had the PCIE_USERCLK1_FREQ set incorrectly at 4 instead of 5.

For an 8x Gen 2, the input parameters for the Pipe_clock.v file should be as follows:

 parameter PCIE_ASYNC_EN      = "FALSE",     // PCIe async enable
 parameter PCIE_TXBUF_EN      = "FALSE",     // PCIe TX buffer enable for Gen1/Gen2 only
 parameter PCIE_CLK_SHARING_EN= "FALSE",     // Enable Clock Sharing
 parameter PCIE_LANE          = 8,           // PCIe number of lanes
 parameter PCIE_LINK_SPEED    = 3,           // PCIe link speed
 parameter PCIE_REFCLK_FREQ   = 0,           // PCIe reference clock frequency
 parameter PCIE_USERCLK1_FREQ = 5,           // PCIe user clock 1 frequency
 parameter PCIE_USERCLK2_FREQ = 4,           // PCIe user clock 2 frequency
 parameter PCIE_OOBCLK_MODE   = 1,           // PCIe oob clock mode
 parameter PCIE_DEBUG_MODE    = 0            // PCIe Debug mode

 

Using these settings allowed to system to boot up without issues.

This leads me to point out that the data sheet PG054 is incorrect.  On page 191, it says the following:

userclk - 62.5 MHz / 125 MHz / 250 MHz clock, depending on selected PCIe core lane width, link speed, and AXI interface width.

 

A value of 5 gives the USERCLK1 a frequency of 500 MHz.  This is not listed as a possible value!  Please fix this so that others may not have the same problem.

 

In addition, it lists only one posibility for the OOBCLK:

 

oobclk – 50 MHz clock

 

The PIO design uses a value of 1, which is equal to 62.50 MHz.  This also should be listed as a possibility in this section.


Thank you for your help.

Mark

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