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Newbie premnath
Newbie
88 Views
Registered: ‎11-12-2018

PCIe Example Design

Hi,

I'm implementing PCIe in Kintex 7 Board, In example design of receiver module the below lines are there, 

req_addr <= region_select(1 downto 0) & m_axis_rx_tdata(10 downto 2) & "00" ;

wr_addr <= region_select(1 downto 0) & m_axis_rx_tdata(10 downto 2) ;

I didn't get why reserved bit (m_axis_rx_tdata(10)) is used?

The data m_axis_rx_tdata(9 downto 0) signifies length of data payload in DW's(32bits) not the address of the data.

rd_addr <= req_addr(12 downto 2) ;

In the above line two LSB's are ignored while considering for read address.

So please kindly explain me in detail regarding this.

 

Thanks in advance,

 

Regards,

Premnath

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1 Reply
Xilinx Employee
Xilinx Employee
40 Views
Registered: ‎08-02-2007

回复: PCIe Example Design

 

 

Hi Premnath

As shown in the screenshot ,the m_axis_rx_tdata can be data or address or other mean depends on the clock cycle and width

in the pio example,  part of PCIE address will be used as part of memory address

 

regards

Iris

 

 
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