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Explorer
Explorer
4,548 Views
Registered: ‎12-02-2012

PCIe PIO example BAR size

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The XTP207, which provides instructions for how to instantiate an example PCIe design for the VC707 eval board, has you set the size of BAR 0 to 1MB. Looking at the PIO code that gets generated in Vivado 2016.2 as part of the example however, the EP_MEM used as the storage backing for BAR 0 is only 8KB in size. Was this discrepancy just due to the age of XTP207 or is the PIO example code actually intended to support a 1MB bar somehow?

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Xilinx Employee
Xilinx Employee
8,441 Views
Registered: ‎11-25-2015

Re: PCIe PIO example BAR size

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Hi @zwabbit

 

Yes the PIO design supports only four discrete target spaces, each consisting of a 2 KB block of memory represented by a separate Base Address Register (BAR).Each of the four 2 KB address spaces represented by the BARs corresponds to one of four

2 KB address regions in the PIO design. Each 2 KB region is implemented using a 2 KB dual-port block RAM. As transactions are received by the core, the core decodes the address and determines which of the four regions is being targeted.

 

It’s seems a limitation with the PIO example design not with the core…

 

For complete details refer “Base Address Register Support” section page 270 in PG054

 

Thanks,

Sethu

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BAR0 2GB.JPG
EP_MEM 8KB.JPG
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2 Replies
Xilinx Employee
Xilinx Employee
8,442 Views
Registered: ‎11-25-2015

Re: PCIe PIO example BAR size

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Hi @zwabbit

 

Yes the PIO design supports only four discrete target spaces, each consisting of a 2 KB block of memory represented by a separate Base Address Register (BAR).Each of the four 2 KB address spaces represented by the BARs corresponds to one of four

2 KB address regions in the PIO design. Each 2 KB region is implemented using a 2 KB dual-port block RAM. As transactions are received by the core, the core decodes the address and determines which of the four regions is being targeted.

 

It’s seems a limitation with the PIO example design not with the core…

 

For complete details refer “Base Address Register Support” section page 270 in PG054

 

Thanks,

Sethu

-----------------------------------------------------------------------------------------------

Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.

 

BAR0 2GB.JPG
EP_MEM 8KB.JPG
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Newbie ronakec99
Newbie
3,458 Views
Registered: ‎03-22-2011

Re: PCIe PIO example BAR size

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Hi @zwabbit

 

I am trying to implement XTP246, ZC706 PCIe Design on the board using PIO design

It works fine as per the given steps in the pdf file, where

 

As per my understanding, The Endpoint core request for 1MB space in HOST memory, 

 

The HOST allocate 1MB space with BAR address to endpoint

 

This endpoint space can be viewed in PCItree utility, where the memory can be write and read

 

Also we try to change the endpoint core from 1MB to 64MB and tested , and found of with  the BAR memory space of 64MB on PCItree

 

So the question is what is the role of PIO in this application ,since in this application there is no such write and read request from host-pc, the PCItree simply do simply write and read on the endpoint bar space

 

The example is on the endpoint asking for the memory space in host-pc, and host-pc allocate the same , which can be seen by PCItree utility. so why PIO is needeed