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Adventurer
Adventurer
11,349 Views
Registered: ‎09-27-2011

PCIe Power & Clock Buffer

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Hello,
I'm updating a companie's PCI card to PCIe and am using a Spartan6.  Targetting the slower 2.5 GHz.  I have two questions regarding design suggestions.

 

A) The first is a transceivers power supply clarification. The documentation stresses how pure this needs to be by even offering geometry which is free from the SelectIO signals. I did not see it explicitly stated, but does this mean that a separate LDO (linear power supply) is recommended for VCCINT then for MGT_AVCC?

 

B) Second question: Been following one of the Xilinx PCIe example designs:
http://www.xilinx.com/support/documentation/boards_and_kits/xtp067_sp605_schematics.pdf
To my surprise it sends the PCIe clock though an external clock buffer ICS874001 to remove jitter which costs $10 to $18 a piece.
http://www.digikey.com/product-search/en?x=-918&y=-73&lang=en&site=us&KeyWords=ICS874001
I understand how this helps. It opens the eye by removing jitter but how necessary is it? Is this adding fuel additive or engine oil? We need a reliable card but not necessarily one that can go 90 mph.

 

Thanks,

~Joshua

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1 Solution

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Scholar kotir
Scholar
19,242 Views
Registered: ‎02-03-2010

Re: PCIe Power & Clock Buffer

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A) Yes, separate regulator is recommended as the VCCINT will have switching noise from all of the fabric logic. The total peak-to-peak noise as measured at the input pin of the FPGA should not exceed 10 mVpk-pk.
if you share regulator with VCCINT...it will be really hard to meet this requirement
This is mentioned in the UG386 (spartan-6 GT user guide)

 

B) Have a look at the AR18329 while clocking the Xilinx PCIe blocks.I agree with your comments that ICS chip acts as jitter attenuator.

http://www.xilinx.com/support/answers/18329.html

 

However this is recommended to make theclock fed to the devicewith in the jitter spec required by MGTs.

 

-KR

    

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3 Replies
Scholar kotir
Scholar
19,243 Views
Registered: ‎02-03-2010

Re: PCIe Power & Clock Buffer

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A) Yes, separate regulator is recommended as the VCCINT will have switching noise from all of the fabric logic. The total peak-to-peak noise as measured at the input pin of the FPGA should not exceed 10 mVpk-pk.
if you share regulator with VCCINT...it will be really hard to meet this requirement
This is mentioned in the UG386 (spartan-6 GT user guide)

 

B) Have a look at the AR18329 while clocking the Xilinx PCIe blocks.I agree with your comments that ICS chip acts as jitter attenuator.

http://www.xilinx.com/support/answers/18329.html

 

However this is recommended to make theclock fed to the devicewith in the jitter spec required by MGTs.

 

-KR

    

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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Adventurer
Adventurer
11,230 Views
Registered: ‎09-27-2011

Re: PCIe Power & Clock Buffer

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One more question, do I need a seperate ground rail for the MGTs?  

 

The last point on page 176 of ug386 says to "Maintain isolation of the return current paths for both the SelectIO signals and the GTP transceiver signals including both traces and vias."

http://www.xilinx.com/support/documentation/user_guides/ug386.pdf

In figure 5:11 ug386 also shows the stackup with the GTP transceiver having two dedicated ground layers.

 

However in the example design xtp067_sp605 the MGT_VCC power supply (shown on page 27 does not show a seperate ground net.

http://www.xilinx.com/support/documentation/boards_and_kits/xtp067_sp605_schematics.pdf

 

Is the MGT ground actually the same net just seperate plan as the SelectIO ground?  If they are the same net, how are they to be tied together without allowing stray currents from sneeking though?  I suppose a single connection at the power supply would prevent stray currents.

 

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Adventurer
Adventurer
11,178 Views
Registered: ‎09-27-2011

Re: PCIe Power & Clock Buffer

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This additional question has been broken out as its own thread.

http://forums.xilinx.com/t5/PCI-Express/PCIe-grounding/td-p/394601

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