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Adventurer
Adventurer
268 Views
Registered: ‎02-22-2016

PCIe Tandem Configuration causes adjacent GTY to fail routing

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Hi,

I have a Ultrascale+ design which includes the XDMA IP core (AXI-bridge configuration, PCIe Gen2 x4) with Tandem PCIe enabled.
The PCIe link uses the GTYs in bank 224 (GTY_CHANNEL_X0Y0 to X0Y3), right next to the PCIe hard block.
Additionally GTY_CHANNEL_X0Y4 and GTY_CHANNEL_X0Y5 are used for two SGMIIs.

When PCIe Tandem Configuration is enabled routing starts to fail for one SGMII GTY.

Nets with Routing Errors:
  GLOBAL_LOGIC0
    Unrouted Pins -- only the first 10 are listed, use -show_all to get the full list:
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/EYESCANRESET
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/EYESCANTRIGGER
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/GTTXRESETSEL
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[0]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[10]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[12]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[14]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[16]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[18]
      sgmii_blk.i_gig_ethernet_pcs_pma_1/U0/transceiver_inst/gig_ethernet_pcs_pma_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_ethernet_pcs_pma_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TSTIN[2]

I think the problem is caused by routing congestion (or impossible routing) due to GTY_CHANNEL_X0Y4 being very close to the stage1 pblock which is automatically created by the XDMA IP for PCIe Tandem Configuration.

It seems to me, the routing matrix (?) INT_INTF_R_TERM_GT_X74Y60/INT_INTF_R_TERM_GT_INTER is overutilized and does not allow any more nets to be routed through it. But that's purely speculative.

In PG156, p.291, I could only find the following paragraph related to GTY restrictions with PCIe and/or Tandem Configuration.

Some PCIe locations have non-ideal GT Quad selections as result of their proximity to the
edge of the device, SLR boundary, or other PCIe blocks. In these scenarios, the most
adjacent GTs may not be optimal for place and route, but will work as desired. The figure
below shows one common example.

I tried to edit the pblock constraints to give some more room for GTY routing, but this did not work out as intended. All my changes seem to get overwritten by the IP constraints.

How can I continue to solve this problem?

I can upload a minimal example design which reproduces this issue, however the file is too large to be attached in the forums.

(Vivado 2018.3 + Windows 10 machine)

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Xilinx Employee
Xilinx Employee
85 Views
Registered: ‎01-30-2019

Re: PCIe Tandem Configuration causes adjacent GTY to fail routing

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Hi @muellera 

As an SR has already been created at Xilinx Technical Support and as I have provided a solution for this issue on SR email thread.

please close this thread.

 

--Suraj 

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4 Replies
Adventurer
Adventurer
234 Views
Registered: ‎02-22-2016

Re: PCIe Tandem Configuration causes adjacent GTY to fail routing

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When I reduce the size of the default Tandem stage1 pblock and then route the design - that is route the remaining unrouted nets - routing succeeds, however I get the following error:

ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net GND (or <const0>) does not honor the contain/exclude routing due to routing nodes:  INT_X65Y60/INODE_W_3_FT1 INT_X65Y60/INODE_W_5_FT1 INT_X65Y60/INT_INT_SDQ_72_INT_OUT0 INT_X65Y60/INT_NODE_SDQ_22_INT_OUT1 INT_X74Y60/INODE_E_5_FT1  
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Adventurer
Adventurer
130 Views
Registered: ‎02-22-2016

Re: PCIe Tandem Configuration causes adjacent GTY to fail routing

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Note that the issue is present for both "PCIe DMA mode" and "AXI-Bridge mode" of the XDMA IP core.

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Xilinx Employee
Xilinx Employee
86 Views
Registered: ‎01-30-2019

Re: PCIe Tandem Configuration causes adjacent GTY to fail routing

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Hi @muellera 

As an SR has already been created at Xilinx Technical Support and as I have provided a solution for this issue on SR email thread.

please close this thread.

 

--Suraj 

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Adventurer
Adventurer
51 Views
Registered: ‎02-22-2016

Re: PCIe Tandem Configuration causes adjacent GTY to fail routing

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I will close this thread based on Suraj's promise that the issue is solved in the upcoming Vivado 2019.2 release.

 

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