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Explorer
Explorer
10,060 Views
Registered: ‎12-01-2010

PCIe core 3.0 - pulse width timing violation

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This was addressed here once before, but the response was off the mark.

 

I have a PCIe design running on the VC707 dev board.    The core is configured to run Gen 2 x8.  (this means a generated user clock of 250MHz)  The design compiles and routes just fine with one and only one exception:  A pulse width violation on USERCLK1.  This clock is internal to the core and i have NO control over it.

I have tried generating the core at Gen 1 x8, and i get the exact same pulse width violation.

I have also generated the core with the clocking external, and that caused even more clocking headaches.

 

What constraints specifically do i need to put into place in order to alieviate this timing violation?

 

PCIe - core pulse width failure.jpg

 

I am using Vivado 2013.4.

Thank you.

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Explorer
Explorer
17,320 Views
Registered: ‎12-01-2010

Re: PCIe core 3.0 - pulse width timing violation

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I believe i have solved my own problem.  The USERCLK that is generated inside the IP core gets sent out to be used in the main user design.  I added a constraint on this output clock thinking that i needed to.

Turns out, since the clock is generated in an MMCM, it is automatically constrained.  My second constraint, even though the same value, seems to have overconstrained this net.

 

Once the additional constraints were removed, the pulse width errors went away!

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1 Reply
Highlighted
Explorer
Explorer
17,321 Views
Registered: ‎12-01-2010

Re: PCIe core 3.0 - pulse width timing violation

Jump to solution

I believe i have solved my own problem.  The USERCLK that is generated inside the IP core gets sent out to be used in the main user design.  I added a constraint on this output clock thinking that i needed to.

Turns out, since the clock is generated in an MMCM, it is automatically constrained.  My second constraint, even though the same value, seems to have overconstrained this net.

 

Once the additional constraints were removed, the pulse width errors went away!

0 Kudos