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Contributor
Contributor
78 Views
Registered: ‎03-21-2010

PCIe link training issue for Artix 7

HI,

  I encounter a PCIe training fail issue for Artix 7A50T. The target PCIe implementation is Gen2x4. The boards plugging into some MBs can be identified as PCIe gen2x4 device. But Some MBs identify it as Gen1x4 or no pcie device.

I had seen  https://www.xilinx.com/support/answers/56616.html and captured some information:

1. Does card is in the normal operation when LTSSM state is 16 -> 1c -> 1d -> 20 -> 16 repeatedly.

ltssm161c1d20.jpg2. When triger on LTSSM is 0x1E, we got below picture and RXCDRLOCK will become low when LTSSM is in  0x1F. Is it normal?

rxcdrlock_low.pngThanks

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3 Replies
Contributor
Contributor
70 Views
Registered: ‎03-21-2010

Re: PCIe link training issue for Artix 7

Another question:

Please see below picture. RXDATA has data bc,4a,00,00,8e,64,4a,00,4a,4a....repeatly. Does 8E(bit7 is 1) mean MB ask to change speed? And who bit 3 is 1. According to the second picture, bit3-5 should be 0.

bc4a.jpgbit8.jpg

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Contributor
Contributor
67 Views
Registered: ‎03-21-2010

Re: PCIe link training issue for Artix 7

And what transceiver's parameters I can modify directly to improve link training issue? Customer said to capture this data don't help anymore. He wants to modify transceiver's parameters directly.

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Xilinx Employee
Xilinx Employee
34 Views
Registered: ‎08-02-2007

Re: PCIe link training issue for Artix 7

 LTSSM will goes to 16 and back to recovery again to change the speed  and then it will go to 16 the second time to be stable in Gen2 Speed

can you check if rxstatus is always 47474 (not 0) it means  there might be some SI issue

make sure the clock is sync to the link partiner 

make sure the eye diagram is good 

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