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Visitor ela.damian
Visitor
287 Views
Registered: ‎12-19-2017

PIPE Version

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Hello, 

 

I've just read the specification of the PHY interface from Intel and was wondering which version of PIPE is implemented for the UltraScale PHY block, as I can not find certain signals (like the message bus interface introduced in PIPE 4.4).  Additionally, when I instantiate it, I can not find the 'width' control signal, which shall set the PIPE data path width. Is it possible to change the width of the data path? Thanks in advance!

 

Best regards, 

Mihaela

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Re: PIPE Version

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The IP is based on PIPE Specification v3.0.We will add this information in the product guide to avoid confusion. Please review the spec and let us know if you have any further questions.

Thanks.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Re: PIPE Version

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The list of supported signals is documented in the PHY product guide. Also, the Gen3/Gen4 TX and RX equalization sequences are different from the PIPE specification. The custom Gen3/Gen4 equalization scheme must be used. Please check the product guide in the link below for the details and let us know if you have any specific questions.

https://www.xilinx.com/support/documentation/ip_documentation/pcie_phy/v1_0/pg239-pcie-phy.pdf

Thanks.

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Visitor ela.damian
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Registered: ‎12-19-2017

Re: PIPE Version

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Hello,

first of all, thanks for your answer! I should have mentioned in the initial post that I have read the Xilinx PHY product guide before posting. However, I did not find in the product guide the signals of the message bus interface and that got me confused. As I know that this message bus interface was introduced in the PIPE specification 4.4, I was wondering to which PIPE version (not PCIe version) does the Xilinx PHY module comply. I hope I did not miss any info while reading the product guide...

Thanks!

 

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Visitor ela.damian
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Registered: ‎12-19-2017

Re: PIPE Version

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I guess the answer to my question is that the PHY module from Xilinx does not implement a low pin count interf.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Re: PIPE Version

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The IP is based on PIPE Specification v3.0.We will add this information in the product guide to avoid confusion. Please review the spec and let us know if you have any further questions.

Thanks.