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Visitor mozi87
Visitor
388 Views
Registered: ‎05-04-2018

Peer-to-peer transaction between physical functions

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Hi, 

As I know, the Xilinx Integrated Block for PCI Express supports a multi-function device, up to two physical functions for UltraScale.

Is it possible to directly transfer data between the physical functions without redirecting to upstream such as switch or root complex (i.e., peer-to-peer transaction between physical functions within the endpoint device)?

 

 

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Xilinx Employee
Xilinx Employee
198 Views
Registered: ‎12-10-2013

Re: Peer-to-peer transaction between physical functions

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- Do you mean that the Integrated Block is possible to transfer data from a function to other function (both in the same endpoint (i.e., FPGA)) with redirecting the transaction to switch or root complex?

Once the data traffic has come through the AXI-Stream interface, you could potentially route that data to the user logic managing that function.  It would not be PCIe transfers, it would be your user logic managing this - because even with multiple functions, the actual FPGA user logic interface is still a single interface.

- In that case, a FPGA will include both a switch and Integrated Block for PCI Express. Am I correct?

Please see above.  We do not currently have an IP internal to the FPGA that is a PCIe switch.  You would be doing the logical transfer interior to the FPGA, not using the PCIe side of the core.

- QDMA Mailboxes

QDMA does indeed have a mailbox mechanism inside the core that allows Mailbox transfers -- however these are not done via PCIe, they are done inside the logic in the FPGA.  This is not the same as PCIe peer-to-peer.

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4 Replies
Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎12-10-2013

Re: Peer-to-peer transaction between physical functions

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On the PCIe interface, internal peer-to-peer functionality is not available in the core.  However, with the Integrated Block, you could transfer back-end traffic or data in the user logic.  For true Peer-to-Peer, you would need a switch capable of this.

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Visitor mozi87
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237 Views
Registered: ‎05-04-2018

Re: Peer-to-peer transaction between physical functions

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Thank you for reply.

 

On the PCIe interface, internal peer-to-peer functionality is not available in the core. 

- OK

However, with the Integrated Block, you could transfer back-end traffic or data in the user logic. 

- Do you mean that the Integrated Block is possible to transfer data from a function to other function (both in the same endpoint (i.e., FPGA)) with redirecting the transaction to switch or root complex?

For true Peer-to-Peer, you would need a switch capable of this.

- In that case, a FPGA will include both a switch and Integrated Block for PCI Express. Am I correct?

 

By the way, I found that a QDMA supports a communication between physical or virtual functions as below:

'Any PF or VF can communicate to a PF (not itself) through mailbox.' (p.24 in PG302)

Is that not a peer-to-peer transaction but redirected transaction to root complex?

 

 

 

 

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Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎12-10-2013

Re: Peer-to-peer transaction between physical functions

Jump to solution

- Do you mean that the Integrated Block is possible to transfer data from a function to other function (both in the same endpoint (i.e., FPGA)) with redirecting the transaction to switch or root complex?

Once the data traffic has come through the AXI-Stream interface, you could potentially route that data to the user logic managing that function.  It would not be PCIe transfers, it would be your user logic managing this - because even with multiple functions, the actual FPGA user logic interface is still a single interface.

- In that case, a FPGA will include both a switch and Integrated Block for PCI Express. Am I correct?

Please see above.  We do not currently have an IP internal to the FPGA that is a PCIe switch.  You would be doing the logical transfer interior to the FPGA, not using the PCIe side of the core.

- QDMA Mailboxes

QDMA does indeed have a mailbox mechanism inside the core that allows Mailbox transfers -- however these are not done via PCIe, they are done inside the logic in the FPGA.  This is not the same as PCIe peer-to-peer.

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Visitor mozi87
Visitor
180 Views
Registered: ‎05-04-2018

Re: Peer-to-peer transaction between physical functions

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Thanks a lot for detailed explanation, bethe.

 

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