We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Newbie scottkeane
Registered: ‎05-27-2018

Petalinux ZCU-102 PS-PCIe MSI-x Interrupts stop

Running under Petalinux using a ZCU102 board with a PS-PCIe root-complex, PCIe MSIx interrupts stop.

 Additional setup on a PCIe peripheral/endpoint involves modifying registers on it via the root-complex. In a previous Linux Zynq based system this is performed by temporarily masking off PCIe interrupts and then setting up the registers. Any incoming MSI-x messages are handled by checking and clearing the PCIe interrupt status bits and reading from a message fifo. The same approach is being tried with the Ultrascale design, however, once the first interrupt is detected and status bits are cleared, no further interrupts are detected by looking at the status bits.

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-06-2008

Re: Petalinux ZCU-102 PS-PCIe MSI-x Interrupts stop

PS-PCIe in RP mode doesn't support MSI-X. The support is available if you are using PL-PCIe in RP mode. The support for latter was added recently only.

Please let us know if you have any questions on above.


0 Kudos