We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer uncle_tim
Registered: ‎12-04-2015

Problems with pcie4_ucale_plus demo design


I am using the ultrascale PCIe core demo design, my bus width is 512 bit.

* As long as I don't attempt bus mastering, everything works fine. I can read and write from the card, everything is stable.

* When I activate the gen_transaction signal, it generates a read transaction and reads 1 DW from computer memory. That also works fine! I see the correct memory values appear on the ILA window.(rc_tdata)

* The trouble starts when I want to read more than 1 DW. As soon as I change the "DWORD Count" in the rq_tdata from 1 to anything else, for example 2 or 4, all hell breaks loose:
The signal user_lnk_up goes down. The device disappears from device manager. I have to reboot my PC.


I do trust my computer, because my old (Virtex-7) DMA engine runs stable and with high performance.

The problems are present with and Vivado 2017.4 and Vivado 2019.1


Any ideas?


Thanks for any help,


Uncle Tim









0 Kudos
2 Replies
Observer uncle_tim
Registered: ‎12-04-2015

Re: Problems with pcie4_ucale_plus demo design - Update


A little update on my problem:

* It also present with 256 bit axi bus

* it is also caused by write transactions. I can write 1 DW but I can't write more than 1.

Uncle Tim

0 Kudos
Observer uncle_tim
Registered: ‎12-04-2015

Re: Problems with pcie4_ucale_plus demo design - Update

This is a short list to reproduce the error:


* Start Vivado 2019.1

* Create a project using the VCU118 board.

* Generate Ultrascale+ PCI Express Integrated Block. Everything default, just

- change device ID

- enable pipe interface (I don't thinks that matters, just for completenes)


* Open example design

* In XDC uncomment line 89 (reset pin)

* Generate bitstream for impl_1. This will be the working bitstream, for comparison


* Go to pio_tx_engine.v line 3080 and change „11'h001“ to „11'h002“ (DWORD Count)

* Create impl_2 and create a bitstream.


Install some driver so you can read from and write to the card.


In the computer software,

- Write 42 to address 0 (Or some other nice number of your choice)

- Read from address 0 → Will return 42

- Write 0xaaaa_bbbb to address 0x3aa, quickly followed by 0

  → this triggers gen_transaction for a short time

- Read from address 0

  → returns 42 on bitstream 1

  → fails on bitstream 2 because the card is no longer present


Remark1: This reads some data from fome fixed, hard coded address. This is not elegant of course, but I wanted to expose the problem with minimal changes in the demo design.

Remark2: It is important to turn on "gen_transaction" only for a short time. Otherwise the card generates too much read requests, at a faster pace than the computer can answer them. This of course leads to an error, independently from the DWORD count.



I can share my designs and drivers and test software, in case anybody cares.


Thanks for reading


Uncle Tim






0 Kudos