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Visitor yinlian0407
Visitor
240 Views
Registered: ‎12-20-2018

Question about MSI Interrupt on 7 series

I config the PCIE core in Interrupt item as this: MSI mode is enabled, Legacy and MSI-X mode are disabled. The singal cfg_interrupt_msienable is high. I follow the pg054 to put cfg_interrupt high. And then the cfg_interrupt_rdy is pulled high. Finaly I put the cfg_interrupt down to finish the MSI.

 

But I find that the cfg_interrupt_msienable is down when windows 10 enable fastboot. The fastboot is a function that windows puts data from ddr memory into HDD when windows is shut down. That means I can't send MSI from EP to the RC.

 

Thanks!

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4 Replies
Moderator
Moderator
161 Views
Registered: ‎02-16-2010

Re: Question about MSI Interrupt on 7 series

@yinlian0407

Do you know if the link up has finished?

Please refer to AR#58495 (https://www.xilinx.com/support/answers/58495.html) to know the steps involved to enable MSI with 7 series PCIe hardblock IP.

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Visitor yinlian0407
Visitor
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Registered: ‎12-20-2018

Re: Question about MSI Interrupt on 7 series

Thanks for your reply.
I have read AR#58495. And I am sure I config the core as the guide.


If the link up you mentioned is the link from PCIE core to PC, I am sure it has completed.
In normal situation, I can see the signal cfg_interrupt_msienable is high.

I shut down the PC with Windows 10, and then make it power on. The signal cfg_interrupt_msienable is low. That means I can not make cfg_interrupt high to send a MSI to PC.


When the fast boot in Windows 10 has been enable, that will happen. If the fast boot has been disable, that will not happen.

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Moderator
Moderator
141 Views
Registered: ‎02-16-2010

Re: Question about MSI Interrupt on 7 series

@yinlian0407

How do you confirm the link up is achieved from PCIE core to PC when fast boot is enabled?

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Visitor yinlian0407
Visitor
136 Views
Registered: ‎12-20-2018

Re: Question about MSI Interrupt on 7 series

Thank you very much for your reply.


When the Windows 10 is power on with fast boot, I can get the TLP from the core and send the TLP to the core. But cfg_interrupt_msienable from the core is low.


According to this, can I confirm the link up is achieved?

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